PI7C8150ND Pericom Semiconductor, PI7C8150ND Datasheet - Page 34

• Manufacturer Part Number: PI7C8150ND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150ND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Case: BGA
• Dc: 04+
• Lead Free Status / Rohs Status: Not Compliant

3.8.1
3.8.2
STOP_L asserted with DEVSEL_L and TRDY_L de-asserted. Indicates that target will
never be able to complete this transaction. DEVSEL_L must be asserted for at least one
cycle during the transaction before the target abort is signaled.
MASTER TERMINATION INITIATED BY PI7C8150
PI7C8150, as an initiator, uses normal termination if DEVSEL_L is returned by target
within five clock cycles of PI7C8150’s assertion of FRAME_L on the target bus. As an
initiator, PI7C8150 terminates a transaction when the following conditions are met:
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If PI7C8150 is delivering posted write data when it terminates the transaction because the
master latency timer expires, it initiates another transaction to deliver the remaining write
data. The address of the transaction is updated to reflect the address of the current DWORD
to be delivered.
If PI7C8150 is pre-fetching read data when it terminates the transaction because the master
latency timer expires, it does not repeat the transaction to obtain more data.
MASTER ABORT RECEIVED BY PI7C8150
If the initiator initiates a transaction on the target bus and does not detect DEVSEL_L
returned by the target within five clock cycles of the assertion of FRAME_L, PI7C8150
terminates the transaction with a master abort. This sets the received-master-abort bit in the
status register corresponding to the target bus.
For delayed read and write transactions, PI7C8150 is able to reflect the master abort
condition back to the initiator. When PI7C8150 detects a master abort in response to a
delayed transaction, and when the initiator repeats the transaction, PI7C8150 does not
respond to the transaction with DEVSEL_L, which induces the master abort condition back
to the initiator. The transaction is then removed from the delayed transaction queue. When
a master abort is received in response to a posted write transaction, PI7C8150 discards the
posted write data and makes no more attempt to deliver the data. PI7C8150 sets the
received-master-abort bit in the status register when the master abort is received on the
primary bus, or it sets the received master abort bit in the secondary status register when
the master abort is received on the secondary interface. When master abort is detected in
posted write transaction with both master-abort-mode bit (bit 5 of bridge control register)
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the
target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data
buffers to the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions,
the master latency timer expires and the PI7C8150’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
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March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150