AD5420AREZ Analog Devices Inc, AD5420AREZ Datasheet - Page 8

• Manufacturer Part Number: AD5420AREZ
• Description: IC DAC 16BIT 1CH SER 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5420AREZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
• Settling Time: 10µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 950mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 16bit
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5410/AD5420
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
TSSOP Pin No.
1, 4, 5, 12
2
3
6
7
8
9
10
11
13
14
15
16
17, 23
NOTES
1. NC = NO CONNECT.
2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.
LFCSP Pin No.
3, 4, 14, 15, 37
39
2
5
6
7
8
9
12, 13
16
17
18
23
1, 10, 11, 19, 20,
21, 22, 24, 30,
31, 32, 33, 34,
35, 38, 40
CLEAR
LATCH
FAULT
SCLK
DV
Figure 5. TSSOP Pin Configuration
SDIN
GND
GND
GND
SDO
GND
GND
CC
10
12
11
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD5410/
AD5420
TOP VIEW
Mnemonic
GND
DV
FAULT
CLEAR
LATCH
SCLK
SDIN
SDO
GND
R
REFOUT
REFIN
DV
SELECT
NC
SET
CC
CC
24
22
20
19
18
17
16
15
14
13
23
21
AV
NC
CAP2
CAP1
BOOST
I
R3
NC
DV
REFIN
REFOUT
R
OUT
SET
DD
SENSE
CC
SELECT
Description
These pins must be connected to ground.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Fault Alert. This pin is asserted low when an open circuit is detected between I
GND or an overtemperature is detected. The FAULT pin is an open-drain output and
must be connected to DV
Active High Input. Asserting this pin sets the output current to the zero-scale value,
which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA
to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.
Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data
into the relevant register. In the case of the data register, the output current is also
updated.
Serial Clock Input. Data is clocked into the input shift register on the rising edge of
SCLK. This operates at clock speeds of up to 30 MHz.
Serial Data Input. Data must be valid on the rising edge of SCLK.
Serial Data Output. This pin is used to clock data from the device in daisy-chain or
readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and
Figure 4.
Ground Reference Pin.
An external, precision, low drift 15 kΩ current setting resistor can be connected to this
pin to improve the overall performance of the device. See the Specifications and
AD5410/AD5420 Features sections.
Internal Reference Voltage Output. V
drift is 1.8 ppm/°C.
External Reference Voltage Input. V
This pin, when connected to GND, disables the internal supply, and an external supply
must be connected to the DV
supply. See the AD5410/AD5420 Features section.
Do not connect to these pins.
Rev. B | Page 8 of 28
NOTES
1. NC = NO CONNECT.
2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.
CC
through a pull-up resistor (typically 10 kΩ).
CLEAR
LATCH
CC
FAULT
SCLK
SDIN
GND
GND
SDO
pin. Leave this pin unconnected to enable the internal
NC
NC
REFIN
10
1
2
3
4
5
6
7
8
9
REFOUT
Figure 6. LFCSP Pin Configuration
= 5 V ± 50 mV for specified performance.
AD5410/AD5420
= 5 V ± 5 mV at T
PIN 1
INDICATOR
(Not to Scale)
TOP VIEW
A
= 25°C. Typical temperature
30 NC
29 CAP2
28 CAP1
27 BOOST
26 I
25 R3
24 NC
23 DV
22 NC
21 NC
OUT
SENSE
CC
SELECT
OUT
and