AD5420AREZ Analog Devices Inc, AD5420AREZ Datasheet - Page 21

• Manufacturer Part Number: AD5420AREZ
• Description: IC DAC 16BIT 1CH SER 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5420AREZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
• Settling Time: 10µs
• Number Of Bits: 16
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 950mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Resolution (bits): 16bit
• Input Channel Type: Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• No. Of Pins: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5410/AD5420 allows the
user to control the rate at which the output current changes.
With the slew rate control feature disabled, the output current
changes at a rate of approximately 16 mA in 10 μs (see Figure 36).
This varies with load conditions. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 14. The parameters are SR clock and SR step.
SR clock defines the rate at which the digital slew is updated,
SR step defines by how much the output value changes at each
update. Both parameters together define the rate of change of
the output current. Table 18 and Table 19 outline the range of
values for both the SR clock and SR step parameters. Figure 41
shows the output current changing for ramp times of 10 ms,
50 ms, and 100 ms.
Table 18. Slew Rate Update Clock Values
SR Clock
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 19. Slew Rate Step Size Options
SR Step
000
001
010
011
100
101
110
111
AD5410 Step Size (LSB)
1/16
1/8
1/4
1/2
1
2
4
8
Update Clock Frequency (Hz)
257,730
198,410
152,440
131,580
115,740
69,440
37,590
25,770
20,160
16,030
10,290
8280
6900
5530
4240
3300
AD5420 Step Size (LSB)
1
2
4
8
16
32
64
128
Rev. B | Page 21 of 28
The time it takes for the output current to slew over a given
output range can be expressed as follows:
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps.
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate. If the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit can be read to check that the
slew has completed before writing to any of the AD5410/
AD5420 registers (see Table 17). The update clock frequency for
any given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Table 20 shows the range of programmable slew times for a full-
scale change on any of the output ranges. The values in Table 20
were obtained using Equation 1. The digital slew rate control
feature results in a staircase formation on the current output, as
shown in Figure 45. Figure 45 also shows how the staircase can
be removed by connecting capacitors to the CAP1 and CAP2
pins, as described in the I
Figure 41. Output Current Slewing Under Control of the Digital Slew Rate
Slew
Step
25
20
15
10
5
0
–10
Size
Time
T
AV
R
A
LOAD
0
DD
= 25°C
×
Update
=
= 24V
10
= 300Ω
Output
10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5
20
Clock
OUT
30
Control Feature
Filtering Capacitors section.
Change
40
Frequency
TIME (ms)
50
60
AD5410/AD5420
×
70
LSB
80
Size
90
100 110
(1)