MAX5393NAUD+ Maxim Integrated Products, MAX5393NAUD+ Datasheet - Page 9

• Manufacturer Part Number: MAX5393NAUD+
• Description: IC POT DGTL DUAL 256TAP 14TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5393NAUD+

• Taps: 256
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resistance In Ohms: 100K
• Number Of Pots: Dual
• Taps Per Pot: 256
• Resistance: 200 Ohms
• Wiper Memory: Volatile
• Digital Interface: Serial (3-Wire, SPI)
• Operating Supply Voltage: 1.7 V to 5.5 V
• Supply Current: 27 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Description/function: Dual Volatile Low Voltage Linear Taper Digital Potentiometer
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2. SPI Digital Interface Format
The MAX5391/MAX5393 dual 256-tap, volatile, low-volt-
age linear taper digital potentiometers offer three end-to-
end resistance values of 10kI, 50kI, and 100kI. Each
potentiometer consists of 255 fixed resistors in series
between terminals H_ and L_. The potentiometer wiper,
W_, is programmable to access any one of the 256 tap
points on the resistor string.
The potentiometers in each device are programmable
independently of each other. The MAX5391/MAX5393
feature an SPI interface.
The MAX5391/MAX5393 contain an internal charge
pump that guarantees the maximum wiper resistance,
R
1.7V. Pins H_, W_, and L_ are still required to be less
than V
allow additional filtering of the charge-pump output, fur-
ther reducing clock feed through that may occur on H_,
W_, or L_. The nominal clock rate of the charge pump
is 600kHz. BYP should remain resistively unloaded as
any additional load would produce a ripple of approxi-
mately I
Pump Feedthrough at W_ vs. C
Operating Characteristics for C
respect to clock feedthrough to the wiper. The value of
Table 1. SPI Register Map
Write Wiper Register B
Write to Both A and B
Bit Number
Bit Name
Write Wiper Register A
WL
, to be less then 200I for supply voltages down to
DD
BYP
+ 0.3V. A bypass input, BYP, is provided to
/(600kHz x C
SCLK
DIN
_______________________________________________________________________________________
CS
STARTED 10-BIT
COMMAND
Detailed Description
BYP
A0
Linear Taper Digital Potentiometers
Dual 256-Tap, Volatile, Low-Voltage
) volts. See the Charge-
BYP
BYP
Charge Pump
sizing guidelines with
A1
graph in the Typical
A1
D7
1
0
0
1
D6
A0
2
0
1
1
D5
D7
D7
D7
D7
3
C
however, C
nicate with the device, nor is there a minimum C
requirement. The maximum wiper impedance specifi-
cation is not guaranteed until the charge pump is fully
settled. See the BYP Ramp vs. C
Operating Characteristics for C
pump settling time.
The MAX5391/MAX5393 include a SPI interface that pro-
vides a 3-wire write-only serial-data interface to control
the wiper tap position through inputs chip select (CS),
data in (DIN), and data clock (SCLK). Drive CS low to
load data from DIN synchronously into the serial shift
register on the rising edge of each SCLK pulse. The
MAX5391/MAX5393 load the last 10 bits of clocked data
into the appropriate potentiometer control register once
CS transitions high. See Figures 2 and 3. Data written
to a memory register immediately updates the wiper
position. Keep CS low during the entire data stream to
prevent the data from being terminated.
The first two bits A1:A0 (address bits) address one of
the two potentiometers. See Table 1. The power-on reset
(POR) circuitry sets the wiper to midscale.
BYP
D4
D6
D6
D6
D6
4
does affect the startup time of the charge pump;
D3
BYP
D5
D5
D5
D5
5
does not impact the ability to commu-
D2
D4
D4
D4
D4
6
D1
D3
D3
D3
D3
7
SPI Digital Interface
WIPER REGISTER
BYP
BYP
D0
LOADED
D2
D2
D2
D2
8
graph in the Typical
impact on charge-
D1
D1
D1
D1
9
D0
D0
D0
D0
10
BYP
9