ISL95810WIU8Z Intersil, ISL95810WIU8Z Datasheet - Page 4

• Manufacturer Part Number: ISL95810WIU8Z
• Description: IC POT DGTL 10K OHM 8-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL95810WIU8Z

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Operating Specifications
EEPROM SPECIFICATIONS
SERIAL INTERFACE SPECIFICATIONS
Hysteresis (Note 13) SDA and SCL Input Buffer Hysteresis
t
Cpin (Note 13)
t
V
DCP
BUF
t
t
Cb (Note 13)
t
t
AA
DH
t
t
t
OL
IN
D
R
V
F
HD:STO:NV
SYMBOL
t
t
t
t
t
t
CC
I
(Note 13)
HD:DAT
SU:STO
HD:STO
(Note 13)
(Note 13)
SU:STA
HD:STA
SU:DAT
(Note 13)
LkgDig
(Note 13)
t
t
(Note 13)
Vpor
(Note 13)
f
HIGH
(Note 13)
(Note 13)
LOW
V
V
SCL
Ramp
IH
IL
Leakage Current, at Pins SDA, SCL,
and WP Pins
DCP Wiper Response Time
Power-On Recall Voltage
V
Power-Up Delay
EEPROM Endurance
EEPROM Retention
WP, SDA, and SCL Input Buffer LOW
Voltage
WP, SDA, and SCL Input Buffer
HIGH Voltage
SDA Output Buffer LOW Voltage,
Sinking 4mA
WP, SDA, and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
STOP Condition Hold Time for Non-
Volatile Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
CC
Ramp Rate
PARAMETER
4
Over the recommended operating conditions unless otherwise specified. (Continued)
Voltage at pin from GND to V
SCL falling edge of last bit of DCP Data Byte to
wiper change
Minimum V
V
completed, and I
Temperature ≤ +75°C
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
following START condition.
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge. Both
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of V
From SCL rising edge crossing 70% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SCL falling edge crossing 30% of V
SDA enters the 30% to 70% of V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
CC
above Vpor, to DCP Initial Value Register recall
ISL95810
CC
TEST CONDITIONS
at which memory recall occurs
2
C Interface in standby state
CC
CC
CC
.
.
.
CC
CC
CC
CC
CC
CC
during a STOP
CC
window.
crossing.
crossing.
CC
CC
CC
CC
CC
CC
window.
, until SDA
.
.
window.
during the
CC
CC
CC
CC
CC
, until
, to
to
to
CC
0.05*V
0.7*V
200,000
0.1 * Cb
0.1 * Cb
1300
1300
20 +
20 +
MIN
-0.3
600
600
600
100
600
600
-10
1.8
0.2
50
10
0
0
2
0
CC
CC
(Note 1)
TYP
V
0.3*V
September 19, 2006
CC
MAX
400
900
250
250
400
2.6
0.4
10
10
50
1
3
+0.3
CC
FN8090.2
UNITS
Cycles
Years
V/ms
kHz
ms
µA
pF
pF
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
V
V
V
V
V