LTC1287CCN8 Linear Technology, LTC1287CCN8 Datasheet - Page 11

• Manufacturer Part Number: LTC1287CCN8
• Description: IC DATA ACQ SYS 12BIT 3V 8-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1287CCN8

• Resolution (bits): 12 b
• Sampling Rate (per Second): 30k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

A
effectively “held” by the sample and hold and will not affect
the conversion result. It is critical that the “–” input voltage
be free of noise and settle completely during the first CLK
cycle of the conversion. Minimizing R
improve settling time. If large “–” input source resistance
must be used the time can be extended by using a slower
CLK frequency. At the maximum CLK frequency of 500kHz,
R
settling.
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settles within the allowed time
SOURCE
PPLICATI
Figure 9. Adequate Settling of Op Amp Driving Analog Input
– < 200 and C2 < 20pF will provide adequate
(–) INPUT
(+) INPUT
D
CLK
OUT
O
CS
U
HORIZONTAL: 500ns/DIV
S
I FOR ATIO
U
W
SOURCE
(+) INPUT MUST SETTLE DURING THIS TIME
t
WHCS
Figure 8c. Setup Time (t
– and C2 will
U
HI-Z
t
SMPL
(see Figures 8a, 8b and 8c). Again the “+” and “–” input
sampling times can be extended as described above to
accommodate slower op amps. For single supply low
voltage application the LT1797 and LT1677 can be made
to settle well even with the minimum settling windows of
6 s (“+” input) and 2 s (“–” input) which occur at the
maximum clock rates (CLK = 500kHz). Figures 9 and 10
show examples of adequate and poor op amp settling. The
LT1077, LT1078 or LT1079 can be used here to reduce
power consumption. Placing an RC network at the output
of the op amps will inprove the settling response and also
reduce the broadband noise.
SUCS
Figure 10. Poor Op Amp Settling Can Cause A/D Errors
) is Not Met
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
HORIZONTAL: 20 s/DIV
B11
LTC1287 F8c
B10
LTC1287
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1287fa