LTC1287CCN8 Linear Technology, LTC1287CCN8 Datasheet - Page 10

• Manufacturer Part Number: LTC1287CCN8
• Description: IC DATA ACQ SYS 12BIT 3V 8-DIP
• Manufacturer: Linear Technology
• Type: Data Acquisition System (DAS)r

Specifications of LTC1287CCN8

• Resolution (bits): 12 b
• Sampling Rate (per Second): 30k
• Data Interface: Serial, Parallel
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC1287
A
“+” Input Settling
The input capacitor is switched onto the “+” input during
the sample phase (t
sample period can be as short as t
as long as t
starts. This variability depends on where CS falls relative
to CLK. The voltage on the “+” input must settle completely
within the sample period. Minimizing R
will improve the settling time. If large “+” input source
10
PPLICATI
(+) INPUT
(–) INPUT
(–) INPUT
(+) INPUT
WHCS
D
D
CLK
CLK
OUT
OUT
CS
CS
O
+ 1.5 CLK cycles before a conversion
SMPL
U
S
, see Figures 8a, 8b and 8c). The
I FOR ATIO
U
(+) INPUT MUST SETTLE DURING THIS TIME
(+) INPUT MUST SETTLE DURING THIS TIME
WHCS
t
WHCS
W
HI-Z
t
WHCS
+ 0.5 CLK cycle or
t
SMPL
SOURCE
HI-Z
t
SMPL
Figure 8a. Setup Time (t
“+” and “–” Input Settling Windows
Figure 8b. Setup Time (t
+ and C1
U
t
SUCS
1ST BIT TEST (–) INPUT MUST
1ST BIT TEST (–) INPUT MUST
SETTLE DURING THIS TIME
SETTLE DURING THIS TIME
resistance must be used, the sample time can be increased
by using a slower CLK frequency. With the minimum
possible sample time of 6.0 s, R
< 20pF will provide adequate settle time.
“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figures 8a,
8b and 8c). During the conversion, the “+” input voltage is
SUCS
SUCS
) is Met
) is Met
B11
B11
B10
B10
SOURCE
LTC1287 F8b
LTC1287 F8a
B9
B9
+ < 4.0k and C1
1287fa