CS5102A-BLZ Cirrus Logic Inc, CS5102A-BLZ Datasheet
CS5102A-BLZ
Specifications of CS5102A-BLZ
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CS5102A-BLZ Summary of contents
Page 1
... Offset and full-scale errors are minimized dur- ing the calibration cycle, eliminating the need for external trimming. The CS5101A and CS5102A each consist of a 2-chan- nel input multiplexer, DAC, conversion and calibration microcontroller, clock generator, comparator, and serial communications port. The inherent sampling architec- ture of the device eliminates the need for an external track-and-hold amplifier ...
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... Output Mode Control ........................................................................................................ 19 4.6.1 Pipelined Data Transmission .............................................................................. 19 4.6.2 Register Burst Transmission (RBT) .................................................................... 20 4.6.3 Synchronous Self-clocking (SSC) ....................................................................... 20 4.6.4 Free Run (FRN) .................................................................................................. 20 5. SYSTEM DESIGN USING THE CS5101A & CS5102A ......................................................... 22 5.1 System Initialization ......................................................................................................... 22 5.2 Single-channel Operation ................................................................................................ 23 6. ANALOG CIRCUIT CONNECTIONS ...................................................................................... 23 6.1 Reference Considerations ............................................................................................... 23 6 ...
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... Figure 12. Charge Settling Time ................................................................................................... 24 Figure 13. CS5101A DNL Plot - Ambient Temperature at 25 °C .................................................. 27 Figure 14. CS5101A DNL Plot - Ambient Temperature at 138 °C ................................................ 27 Figure 15. CS5102A DNL Plot - Ambient Temperature at 25 °C .................................................. 27 Figure 16. CS5102A DNL Plot - Ambient Temperature at 138 °C ................................................ 27 Figure 17. CS5101A DNL Error Distribution.................................................................................. 28 Figure 18 ...
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... Drift (Note (Note Drift (Note 2) - (Note (Note (Note 4) Unipolar Mode - Bipolar Mode - CS5101A CS5102A CS5101A-B Typ Max Min Typ Max -40 to +85 0.002 0.003 - 0.002 0.003 0.001 0.002 - 0.001 0.002 ±¼ ±¼ ±1 ±4 - ±1 ±4 ±1 ±3 - ±1 ±3 ± ...
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... CS5101A-J Symbol Min - - - - - (Note (Note (Note (Note 8) f 100 tp (Note (Note 9, Note 10 (Note 11) PSR - PSR - CS5101A CS5102A CS5101A-B Typ Max Min Typ Max 0 to +70 - 100 - - 100 - 320 425 - 320 425 200 265 - 200 265 - 8. 8. 100 - - -21 -28 - -21 -28 11 ...
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... These timings are for PDT and RBT modes. HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for t CS5101A CS5102A = 50 pF). L Min Typ Max ...
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... ANALOG CHARACTERISTICS, CS5102A (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 4.5V; Full-scale Input Sine Wave, 200 Hz; CLKIN = 1.6 MHz kSps; Bipolar Mode; FRN Mode; AIN1 and AIN2 tied together, each channel tested separately; Analog Source Impedance = 50 Ω with 1000 pF to AGND unless otherwise specified) ...
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... This delay will not exceed 1 master clock cycle + 140 ns. 18. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge. FRN mode allows 9 cycles for fine charge which provides for the minimum 5.625 µs with a 1.6 MHz clock, however; in PDT, RBT, or SSC modes and at clock frequencies of less than 1 ...
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... SWITCHING CHARACTERISTICS, CS5102A (TA = TMIN to TMAX; VA+, VD ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C Parameter CLKIN Period CLKIN Low Time CLKIN High Time Crystal Frequency SLEEP Rising to Oscillator Stable RST Pulse Width RST to STBY falling RST Rising to STBY Rising CH1/2 Edge to TRK1, TRK2 Rising ...
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... drsh 1 1 dfsh4 a. FRN Mode lri Channel Selection Timing Figure 1. Reset, Calibration, and Control Timing 10 t rst STBY t drrs Reset and Calibration Timing 1 Control Output Timing CS5101A CS5102A t dfsh2 t drsh t dfsh1 b. PDT, RBT Mode Start Conversion Timing DS45F6 ...
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... PDT Mode t dhs (Note 28) t dts t slkl t slkh rsclk CS5101A t rsdl CS5102A t rsdl t CS5101A hfs t CS5102A hfs t dhlri falling when SCLK is low. If SCLK is high when CS5101A CS5102A = 50 pF). L Min Typ Max 200 - - 100 150 - 140 230 - 65 125 - 2t - clk - 2t - clk 2t -100 ...
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... SCLK Input (PDT & RBT Modes dhs Pipelined Data Transmission (PDT chfs rsclk t slkl sclk SCLK Output (FRN & SSC Modes) Serial Data Timing Register Burst Transmission (RBT) Data Transmission Timing Figure 2. Serial Communication Timing CS5101A CS5102A slkh d ss rsd LSB dss DS45F6 ...
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... DC Power Supplies: 31. All voltages with respect to ground. 32. The CS5101A and CS5102A can accept input voltages up to the analog supplies (VA+ and VA-). They will produce an output of all 1s for input above VREF and all 0s for inputs below AGND in unipolar mode, and -VREF in bipolar mode, with binary coding (CODE = low). ...
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... WARNING: Operation beyond these limits may result in permanent damage to the device Symbol (Note 33) Positive Digital VD+ Negative Digital VD- Positive Analog VA+ VA- (Note 34 (AIN and VREF pins) V INA V IND stg CS5101A CS5102A Min Typ Max -0.3 - 6.0 0.3 - -6.0 -0.3 - 6.0 0.3 -6 ±10 (VA-) - 0.3 - (VA+) + 0.3 -0.3 - (VA+) + 0.3 ...
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... A/D converters. The devices include an inherent sample/hold and an on-chip analog switch for 2- channel operation. Both channels can thus be sampled and converted at rates kSps each (CS5101A kSps each (CS5102A). Al- ternatively, each of the devices can be operated as a single channel ADC operating at 100 kSps (CS5101A kSps (CS5102A). ...
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... Calibration The ability of the CS5101A or the CS5102A to con- vert accurately to 16-bits clearly depends on the accuracy of its comparator and DAC. Each device utilizes an “auto-zeroing” scheme to null errors in- troduced by the comparator. All offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the input signal when a conversion is initiated ...
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... CS5101A can slew at 4V/µs. With a full-scale input step, the coarse-charge in- put buffer of the CS5102A will charge the capacitor array within 1% in 3.75 µs. The converter timing al- lows 6 clock cycles for coarse charge settling time. When in fine-charge mode, the CS5102A can slew at 0.4 V/µ ...
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... CS5101A, at least 750 ns of coarse-charge, followed by 1.125 µs of fine-charge is required before initiating a conversion. If coarse charge is not invoked, then µs should be allowed after a step change input for proper acqui- sition. To get an accurate sample using the CS5102A, at least 3.75 µs of coarse-charge, fol onv. S tatus ...
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... LSB +0.5 LSB <(+0.5 LSB) 4.6 Output Mode Control The CS5101A and CS5102A can be configured in three different output modes, as well as an internal, synchronous loop-back mode. This allows great flexibility for design into a wide variety of systems. The operating mode is selected by setting the ...
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... The SSH/SDL goes low coincident with the first falling edge of SCLK, and returns high 2 CLKIN cy- cles after the last rising edge of SCLK. This signal frames the 16 data bits and is useful for interfacing to shift registers (e.g. 74HC595 DSP serial ports racking onverting CS5101A CS5102A Free Run (FRN racking DS45F6 ...
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... ( ( rtin tatu ( ( Figure 6. Register Burst Transmission (RBT) Mode Timing ( ( ( rtin tatu ( Figure 7. Synchronous Self-clocking (SSC) Mode Timing ( rtin tatu ( DS45F6 ckin rtin ata ckin rtin cking rtin Figure 8. Free Run (FRN) Mode Timing CS5101A CS5102A rac kin ata ckin ckin ...
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... SYSTEM DESIGN USING THE CS5101A & CS5102A Figure 9 shows a general system connection diagram for the CS5101A and CS5102A tro lta fere log urce /( rform Figure 9. CS5101A/CS5102A System Connection Diagram 5.1 System Initialization Upon power up, the CS5101A and CS5102A must be reset to guarantee a consistent starting condi- tion and to initially calibrate the device ...
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... References for the CS5012A / CS5014 /CS5016 / CS5101A/ CS5102A / CS5126 Series of A/D Con verters is available for the CS5101A and CS5102A. In addition to working through a refer- ence circuit design example, it offers several built- and-tested reference circuits. During conversion, each capacitor of the calibrated capacitor array is switched between VREF and AGND in a manner determined by the successive- approximation algorithm ...
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... During fine-charge, the charge then settles to the accurate unbuffered version. Fine-charge settling is specified as a maximum of 1.125 µs (CS5101A) or 5.625 µs (CS5102A) for an analog source impedance of less than 50 Ω. In ad- dition, the comparator requires a source imped- ance of less than 400 Ω around 2 MHz for stability. ...
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... The sys- tem connection diagram (Figure 9) shows a decoupling scheme which allows the CS5101A and CS5102A to be powered from a single set of 5V rails. The positive digital supply is derived from the analog supply through a 10 Ω resistor to avoid the analog supply dropping below the digital sup- ply ...
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... CS5101A at 25 °C. Figure 14 illustrates the DNL of the CS5101A at 138 °C ambient after cali- bration at 25 °C ambient. Figure 15 and Figure 16 illustrate the DNL of the CS5102A at 25 °C and 138 °C ambient, respectively. A histogram test is a statistical method of deriving an A/D converter's differential nonlinearity ...
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... Figure 14. CS5101A DNL Plot - Ambient Temperature at 138 ° 25°C A +1 Figure 15. CS5102A DNL Plot - Ambient Temperature at 25 ° 138 °C, CAL @ 25 ° +1 Figure 16. CS5102A DNL Plot - Ambient Temperature at 138 °C DS45F6 CS5101A CS5102A 32,768 Codes 32,768 ...
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... FFT Tests and Windowing In the factory, the CS5101A and CS5102A are tested using Fast Fourier Transform (FFT) tech- niques to analyze the converters' dynamic perfor- mance. A pure sine wave is applied to the device, and a “time record” of 1024 samples is captured and processed. The FFT algorithm analyzes the 28 Figure 17 ...
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... Figures 21 and 22 illustrate that the CS5102A typically yields 92 dB S/(N+D) and 0.001% THD even with a large change in ambient temperature. Unlike conventional successive-ap- proximation ADC's, the signal-to-noise and dy- namic range of the CS5101A and CS5102A are 29 ...
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... Sampling Distortion Like most discrete sample/hold amplifier designs, the inherent sample/hold of the CS5101A and CS5102A exhibits a frequency-dependent distor- tion due to non-ideal sampling of the analog input voltage. The calibrated capacitor array used during conversions is also used to track and hold the an- alog input signal ...
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... All analog circuitry in the CS5101A and CS5102A is wideband in order to achieve fast conversions and high throughput. Wideband noise in the CS5101A and CS5102A integrates to 35 µV rms in unipolar mode (70 µV rms in bipolar mode). This is approximately 1/2 LSB rms with a 4.5V reference in both modes. Figure 23 shows a histogram plot of output code occurrences obtained from 8192 sam- ples taken from a CS5101A in the bipolar mode ...
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... Any offsets are stored on the capacitor array and are effectively subtracted once conversion is initiated. Figure 25 shows pow- er supply rejection of the CS5101A and CS5102A in the bipolar mode with the analog input grounded and a 300 mV p-p ripple applied to each supply. ...
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... STBY DGND VD+ TRK1 TRK2 CRS/FIN SSH/SDL Figure 26. CS5101A & CS5102A 28-pin PLCC Pinout 8.1 Power Supply Connections VD+ - Positive Digital Power, PIN 7 Positive digital power supply. Nominally +5 volts. VD- - Negative Digital Power, PIN 1. Negative digital power supply. Nominally -5 volts. DGND - Digital Ground, PIN 6. ...
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... Digital Inputs HOLD - Hold, PIN 12. A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run Mode, HOLD is disabled, and should be tied to DGND or VD+. ...
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... Serial data changes status on a falling edge of this input, and is valid on a rising edge. When SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A generates its own serial clock at ¼ the master clock frequency and SCLK is an output. ...
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... Units in nanoseconds. Aperture Jitter The range of variation in the aperture time. Effectively the “sampling window” which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. Units in picoseconds. 36 CS5101A CS5102A DS45F6 ...
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... JEDEC # : MS-047 AA-AF Controlling Dimension is Inches CS5101A CS5102A e D2/ MILLIMETERS MIN NOM MAX 4.191 4.3815 4.572 2.286 2.667 3.048 0.4318 0.533 12.446 12.573 11 ...
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... CS5102A-BLZ (lead free) 12. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS5101A-JL8 CS5101A-JL8Z (lead free) CS5101A-BL8 CS5101A-BL8Z (lead free) CS5102A-JL CS5102A-JLZ (lead free) CS5102A-BL CS5102A-BLZ (lead free) * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 38 Temperature Conversion Time 0.003 0 to +70 °C 0.002 -40 to +85 °C 0.003 0 to +70 ° ...
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... Corrected table heading on Page 6. Minor edits, added lead-free device ordering information removed obsolete packages, corrected lead-free device information Added MSL, reflow temp, & floor life specifications. Corrected Linearity Error mislabeled in Characteristics & Specifications as “Dif- ferential Input Range”. www.cirrus.com CS5101A CS5102A Changes 39 ...