AD7680ARMZ Analog Devices Inc, AD7680ARMZ Datasheet - Page 6

• Manufacturer Part Number: AD7680ARMZ
• Description: IC ADC 16BIT LP 100KSPS 8MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7680ARMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 100kSPS
• Input Channel Type: Single Ended
• Supply Current: 5.2mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7680
TIMING SPECIFICATIONS
Table 4. V
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
See Power vs. Throughput Rate section.
3
3
4
8
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
2
5
DD
= 2.5 V to 5.5 V; T
Limit at T
3 V
250
2.5
20 × t
100
10
10
48
120
0.4 t
0.4 t
10
45
1
SCLK
SCLK
SCLK
MIN
5 V
250
2.5
20 × t
100
10
10
35
80
0.4 t
0.4 t
10
35
1
, T
MAX
SCLK
SCLK
A
SCLK
= T
MIN
1
Unit
kHz min
MHz max
min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs typ
to T
Figure 2. Load Circuit for Digital Output Timing Specification
MAX
, unless otherwise noted.
TO OUTPUT
Description
Minimum quiet time required between bus relinquish and start of next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA high impedance
Power up time from full power-down
PIN
50pF
Rev. 0 | Page 6 of 20
C
L
200µA
200µA
I
I
OL
OH
1.6V
8
, quoted in the timing characteristics is the true bus relinquish
DD
) and timed from a voltage level of 1.6 V.