AD7680ARMZ Analog Devices Inc, AD7680ARMZ Datasheet - Page 15

• Manufacturer Part Number: AD7680ARMZ
• Description: IC ADC 16BIT LP 100KSPS 8MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7680ARMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 100kSPS
• Input Channel Type: Single Ended
• Supply Current: 5.2mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDATA
POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered
down between each conversion, or a series of conversions may
be performed at a high throughput rate, and then the ADC is
powered down for a relatively long duration between these
bursts of several conversions. When the AD7680 is in
power-down, all analog circuitry is powered down.
To enter power-down, the conversion process must be
interrupted by bringing CS high anywhere after the second
falling edge of SCLK and before the 10th falling edge of SCLK
as shown in Figure 17. Once CS has been brought high in this
window of SCLKs, the part enters power-down, the conversion
that was initiated by the falling edge of CS is terminated, and
SDATA goes back into three-state. If CS is brought high before
the second SCLK falling edge, the part remains in normal mode
and will not power down. This avoids accidental power-down
due to glitches on the CS line.
SCLK
CS
1
THE PART BEGINS
TO POWER UP
SDATA
SCLK
CS
INVALID DATA
10
1
t
POWER UP
2
Figure 17. Entering Power-Down Mode
Figure 18. Exiting Power-Down Mode
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In order to exit this mode of operation and power up the
AD7680 again, a dummy conversion is performed. On the
falling edge of CS , the device begins to power up and continues
to power up as long as CS is held low until after the falling edge
of the 10th SCLK. The device is fully powered up once at least
16 SCLKs (or approximately 6 µs) have elapsed and valid data
results from the next conversion as shown in Figure 18. If CS is
brought high before the 10th falling edge of SCLK, regardless of
the SCLK frequency, the AD7680 goes back into power-down
again. This avoids accidental power-up due to glitches on the CS
line or an inadvertent burst of 8 SCLK cycles while CS is low. So
although the device may begin to power-up on the falling edge
of CS , it powers down again on the rising edge of CS as long as
it occurs before the 10th SCLK falling edge.
10
1
THE PART IS FULLY POWERED
UP WITH V
THREE-STATE
IN
FULLY ACQUIRED
VALID DATA
20
20
AD7680