AD7680ARMZ Analog Devices Inc, AD7680ARMZ Datasheet - Page 14

• Manufacturer Part Number: AD7680ARMZ
• Description: IC ADC 16BIT LP 100KSPS 8MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7680ARMZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 100kSPS
• Input Channel Type: Single Ended
• Supply Current: 5.2mA
• Digital Ic Case Style: SOP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7680
MODES OF OPERATION
The mode of operation of the AD7680 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
two possible modes of operation, normal and power-down. The
point at which CS is pulled high after the conversion has been
initiated determines whether or not the AD7680 enters power-
down mode. Similarly, if the AD7680 is already in power-down,
CS can control whether the device returns to normal operation
or remains in power-down. These modes of operation are
designed to provide flexible power management options. These
options can optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
This mode provides the fastest throughput rate performance,
because the user does not have to worry about the power-up
times with the AD7680 remaining fully powered all the time.
Figure 16 shows the general diagram of the operation of the
AD7680 in this mode.
SDATA
SCLK
CS
1
4 LEADING ZEROS + CONVERSION RESULT
Figure 16. Normal Mode Operation
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The conversion is initiated on the falling edge of CS as described
in the Serial Interface section. To ensure that the part remains
fully powered up at all times, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS .
If CS is brought high any time after the 10th SCLK falling edge,
but before the 20th SCLK falling edge, the part remains
powered up, but the conversion is terminated and SDATA goes
back into three-state. At least 20 serial clock cycles are required
to complete the conversion and access the complete conversion
result. In addition, a total of 24 SCLK cycles accesses four
trailing zeros. CS may idle high until the next conversion or
may idle low until CS returns high sometime prior to the next
conversion, effectively idling CS low.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
t
10
QUIET
, has elapsed by bringing CS low again.
20