MAX11646EUA+ Maxim Integrated Products, MAX11646EUA+ Datasheet - Page 12

• Manufacturer Part Number: MAX11646EUA+
• Description: IC ADC 10BIT I2C 94.4KSPS 8UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX11646EUA+

• Number Of Bits: 10
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 362mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Number Of Adc Inputs: 2
• Conversion Rate: 1 Ksps to 94.4 Ksps
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: I2C
• Snr: 60 dB
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Power Dissipation: 362 mW
• Maximum Operating Temperature: + 85 C
• Input Voltage: 4.5 V to 5.5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Low-Power, 1-/2-Channel, I
in Ultra-Tiny 1.9mm x 2.2mm Package
The SGL/DIF of the configuration byte configures the
MAX11646/MAX11647 analog input circuitry for single-
ended or differential inputs (Table 2). In single-ended
mode (SGL/DIF = 1), the digital conversion results are
the difference between the analog input selected by
CS0 and GND (Table 3). In differential mode (SGL/
DIF = 0), the digital conversion results are the differ-
ence between the + and the - analog inputs selected
by CS0 (Table 4).
When operating in differential mode, the BIP/UNI bit of
the setup byte (Table 1) selects unipolar or bipolar
operation. Unipolar mode sets the differential input
range from 0 to V
input in unipolar mode causes the digital output code
to be zero. Selecting bipolar mode sets the differential
input range to ±V
ry in unipolar mode and two’s complement in bipolar
mode. See the Transfer Functions section.
In single-ended mode, the MAX11646/MAX11647
always operate in unipolar mode irrespective of
BIP/UNI. The analog inputs are internally referenced to
GND with a full-scale input range from 0 to V
The MAX11646/MAX11647 feature a 2-wire interface
consisting of a serial-data line (SDA) and serial-clock line
(SCL). SDA and SCL facilitate bidirectional communica-
tion between the MAX11646/MAX11647 and the master
at rates up to 1.7MHz. The MAX11646/MAX11647 are
slaves that transfer and receive data. The master (typi-
cally a microcontroller) initiates data transfer on the bus
and generates the SCL signal to permit that transfer.
SDA and SCL must be pulled high. This is typically done
with pullup resistors (750Ω or greater) (see the Typical
Operating Circuit ). Series resistors (R
They protect the input architecture of the MAX11646/
MAX11647 from high voltage spikes on the bus lines,
minimize crosstalk, and undershoot of the bus signals.
One data bit is transferred during each SCL clock
cycle. A minimum of 18 clock cycles are required to
transfer the data in or out of the MAX11646/
MAX11647. The data on SDA must remain stable dur-
ing the high period of the SCL clock pulse. Changes in
SDA while SCL is stable are considered control signals
(see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not busy.
12
______________________________________________________________________________________
Single-Ended/Differential Input
REF
REF
/2. The digital output code is bina-
. A negative differential analog
2-Wire Digital Interface
Unipolar/Bipolar
S
) are optional.
Bit Transfer
REF
.
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP condi-
tion (P), a low-to-high transition on SDA while SCL is high
(Figure 5). A repeated START condition (Sr) can be used
in place of a STOP condition to leave the bus active and
the mode unchanged (see the HS Mode section).
Data transfers are acknowledged with an acknowledge
bit (A) or a not-acknowledge bit (A). Both the master
and the MAX11646/MAX11647 (slave) generate
acknowledge bits. To generate an acknowledge, the
receiving device must pull SDA low before the rising
edge of the acknowledge-related clock pulse (ninth
pulse) and keep it low during the high period of the
clock pulse (Figure 6). To generate a not-acknowledge,
the receiver allows SDA to be pulled high before the
rising edge of the acknowledge-related clock pulse
and leaves SDA high during the high period of the
clock pulse. Monitoring the acknowledge bits allows for
detection of unsuccessful data transfers. An unsuc-
cessful data transfer happens if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should
reattempt communication at a later time.
Figure 5. START and STOP Conditions
Figure 6. Acknowledge Bits
SDA
SCL
SDA
SCL
2
C, 10-Bit ADCs
S
S
1
START and STOP Conditions
2
Sr
NOT ACKNOWLEDGE
Acknowledge Bits
ACKNOWLEDGE
8
P
9