AD9245BCPZ-80 Analog Devices Inc, AD9245BCPZ-80 Datasheet - Page 18

• Manufacturer Part Number: AD9245BCPZ-80
• Description: IC ADC 14BIT 80MSPS 3V 32-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9245BCPZ-80

• Data Interface: Parallel
• Number Of Bits: 14
• Sampling Rate (per Second): 80M
• Number Of Converters: 3
• Power Dissipation (max): 414mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 80MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.7V To 3.6V
• Supply Current: 122mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9245BCP-80EBZ - BOARD EVAL FOR AD9245BCP-80AD9245BCP-40EBZ - BOARD EVAL FOR AD9245BCP-40AD9245BCP-20EBZ - BOARD EVAL FOR AD9245BCP-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9245
THEORY OF OPERATION
The AD9245 architecture consists of a front-end sample-and-
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The pipelined ADC is divided into three sections
consisting of a 4-bit first stage followed by eight 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined into a final 14-bit result
in the digital correction logic. The pipelined architecture
permits the first stage to operate on a new input sample, while
the remaining stages operate on preceding samples. Sampling
occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be
ac-coupled or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of
the output voltage swing. During power-down, the output
buffers go into a high impedance state.
ANALOG INPUT AND REFERENCE OVERVIEW
The analog input to the AD9245 is a differential switched-
capacitor SHA that has been designed for optimum performance
while processing a differential input signal. The SHA input can
support a wide common-mode range (VCM) and maintain
excellent performance, as shown in Figure 38. An input
common-mode voltage of midsupply minimizes signal-
dependent errors and provides optimum performance.
100
95
90
85
80
75
70
65
60
55
50
0.5
Figure 38. AD9245-80 SNR/SFDR vs. Common-Mode Level
1.0
COMMON-MODE LEVEL (V)
SFDR (2.5MHz)
SFDR (39MHz)
1.5
SNR (2.5MHz)
SNR (39MHz)
2.0
2.5
3.0
Rev. D | Page 18 of 32
Referring to Figure 39, the clock signal alternately switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. In addition, a small shunt capacitor
can be placed across the inputs to provide dynamic charging
currents. This passive network creates a low-pass filter at the
ADC’s input; therefore, the precise values are dependent upon
the application. In IF undersampling applications, any shunt
capacitors should be reduced or removed. In combination with
the driving source impedance, they would limit the input
bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, that define the
span of the ADC core. The output common mode of the
reference buffer is set to midsupply, and the REFT and REFB
voltages and span are defined as:
The previous equations show that the REFT and REFB voltages
are symmetrical about the midsupply voltage, and, by definition,
the input span is twice the value of the VREF voltage.
The internal voltage reference can be pin strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section.
Maximum SNR performance is achieved with the AD9245 set
to the largest input span of 2 V p-p. The relative SNR degradation
is 3 dB when changing from 2 V p-p mode to 1 V p-p mode.
VIN+
VIN–
REFT = ½ (AVDD + VREF)
REFB = ½ (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
C
C
PAR
PAR
Figure 39. Switched-Capacitor SHA Input
T
T
5pF
5pF
T
T
H
H