AD9878BSTRL Analog Devices Inc, AD9878BSTRL Datasheet - Page 24

• Manufacturer Part Number: AD9878BSTRL
• Description: IC FRONT-END MIXED-SGNL 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9878BSTRL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 4
• Power (watts): 673mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Not Compliant

AD9878
interface. The Tx gain control select bit in Register 0x0F changes
the interpretation of the bits in Register 0x13, Register 0x17,
Register 0x1B, and Register 0x1F. See Figure 28 and the
Cable-Driver Gain Control section.
Data transfers to the programmable gain cable-driver amplifier
are initiated by the following conditions:
•
•
•
•
OSCIN CLOCK MULTIPLIER
The AD9878 can accept either an input clock into the OSCIN
pin or a fundamental-mode crystal across the OSCIN and
XTAL pins as the device’s main clock source. The internal PLL
then generates the f
signals are derived. The DAC uses f
For DDS applications, the carrier is typically limited to about
CA_DATA
CA_CLK
CA_EN
Power-Up and Hardware Reset: Upon initial power-up and
every hardware reset, the AD9878 clears the contents of the
gain control registers to 0, which defines the lowest gain
setting of the AD832x. Thus, the AD9878 writes all 0s out
of the 3-wire cable amplifier control interface.
Software Reset: Writing a 1 to Bit 5 of Address 0x00 initiates
a software reset. Upon a software reset, the AD9878 clears
the contents of the gain control registers to 0 for the lowest
gain and sets the profile select to 0. The AD9878 writes all 0s
out of the 3-wire cable amplifier control interface if the
gain is previously on a different setting (different from 0).
Change in Profile Selection: The AD9878 samples the
PROFILE input pin together with the two profile select bits
and writes to the AD832x gain control registers when a
change in profile and gain is determined. The data written
to the cable-driver amplifier comes from the AD9878 gain
control register associated with the current profile.
Write to the AD9878 Cable-Driver Amplifier Control
Registers: The AD9878 writes gain control data associated
with the current profile to the AD832x when the selected
AD9878 cable-driver amplifier gain setting is changed. Once
a new, stable gain value is detected (48 to 64 MCLK cycles
after initiation) a data write starts with CA_EN going low.
The AD9878 always finishes a write sequence to the cable-
driver amplifier once it is started. The logic controlling data
transfers to the cable-driver amplifier uses up to
200 MCLK cycles and is designed to prevent erroneous
write cycles from occurring.
8
t
Figure 28. Cable Amplifier Interface Timing
MCLK
MSB
SYSCLK
8
signal from which all other internal
t
MCLK
SYSCLK
4
t
MCLK
4
t
MCLK
as its sampling clock.
LSB
8
t
MCLK
Rev. A | Page 24 of 36
30% of f
above 216 MHz. The OSCIN multiplier function maintains
clock integrity, as evidenced by the part’s excellent phase noise
characteristics and low clock-related spur in the output spectrum.
External loop filter components, consisting of a series resistor
(1.3 kΩ) and capacitor (0.01 µF), provide the compensation
zero for the OSCIN multiplier PLL loop. The overall loop
performance is optimized for these component values.
CLOCK AND OSCILLATOR CIRCUITRY
The AD9878’s internal oscillator generates all sampling clocks
from a simple, low cost, parallel resonance, fundamental fre-
quency quartz crystal. Figure 29 shows how the quartz crystal is
connected between OSCIN (Pin 61) and XTAL (Pin 60) with
parallel resonant load capacitors, as specified by the crystal
manufacturer. The internal oscillator circuitry can also be
overdriven by a TTL-level clock applied to OSCIN with
XTAL left unconnected.
An internal PLL generates the DAC sampling frequency, f
by multiplying the OSCIN frequency by M. The MCLK signal
(Pin 23), f
An external PLL loop filter (Pin 57), consisting of a series resistor
and ceramic capacitor (Figure 29: R1 = 1.3 kΩ, C12 = 0.01 µF),
is required for stability of the PLL. Also, a shield surrounding
these components is recommended to minimize external noise
coupling into the PLL’s voltage-controlled oscillator input (guard
trace connected to AVDDPLL).
Figure 23 shows that ADCs are either sampled directly by a
low jitter clock at OSCIN or by a clock that is derived from the
PLL output. Operating modes can be selected in Register 0x08.
Sampling the ADCs directly with the OSCIN clock requires that
MCLK is programmed to be twice the OSCIN frequency.
PROGRAMMABLE CLOCK OUTPUT REFCLK
The AD9878 provides an auxiliary output clock on Pin 69,
REFCLK. The value of the MCLK divider bit field, R, determines
its output frequency, as shown in the following equations:
In its default setting (0x00 in Register 0x01), the REFCLK pin
provides a buffered output of f
f
f
f
f
f
OSCIN
SYSCLK
REFCLK
REFCLK
MCLK
SYSCLK
MCLK
=
=
. For a 65 MHz carrier, the system clock required is
=
=
=
, is derived by dividing f
f
f
OSCIN
MCLK
f
f
f
OSCIN
OSCIN
MCLK
×
×
,
×
R
for
M
M
M
,
for
4
R
=
R
OSCIN
0
=
2
.
to
63
SYSCLK
by 4.
SYSCLK
,