AD9878BSTRL Analog Devices Inc, AD9878BSTRL Datasheet - Page 18

• Manufacturer Part Number: AD9878BSTRL
• Description: IC FRONT-END MIXED-SGNL 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9878BSTRL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 4
• Power (watts): 673mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Not Compliant

AD9878
SERIAL INTERFACE FOR REGISTER CONTROL
The AD9878 serial port is a flexible, synchronous, serial
communications port that allows easy interface to many
industry-standard microcontrollers and microprocessors.
The interface allows read/write access to all registers that
configure the AD9878. Single or multiple byte transfers are
supported. Also, the interface can be programmed to read words
either MSB first or LSB first. The AD9878 serial interface port
I/O can be configured to have one bidirectional I/O (SDIO)
pin, or two unidirectional I/O (SDIO/SDO) pins.
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases of a communication cycle with the AD9878.
Phase 1 is the instruction cycle, which is the writing of an in-
struction byte into the AD9878, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9878
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is a read or write, the number of bytes in the data transfer,
and the starting register address for the first byte of the data
transfer. The first eight SCLK rising edges of each communication
cycle are used to write the instruction byte into the AD9878.
The eight remaining SCLK edges are for Phase 2 of the commu-
nication cycle. Phase 2 is the actual data transfer between the
AD9878 and the system controller. Phase 2 of the communication
cycle is a transfer of one to four data bytes, as determined by the
instruction byte. Normally, using one multibyte transfer is the
preferred method. However, single-byte data transfers are useful
to reduce CPU overhead when register access requires only one
byte. Registers change immediately upon writing to the last bit
of each transfer byte.
INSTRUCTION BYTE
The R/W bit of the instruction byte determines whether a read
or a write data transfer occurs after the instruction byte write.
Logic high indicates a read operation; logic low indicates a write
operation. The [N1:N0] bits determine the number of bytes to
be transferred during the data transfer cycle. The bit decodes
are shown in Table 9. The timing diagrams are shown in Figure 19
and Figure 20.
Table 8. Instruction Byte Information
MSB 17
R/W
16
N1
15
N0
14
A4
13
A3
12
A2
11
A1
LSB 10
A0
Rev. A | Page 18 of 36
Table 9. Bit Decodes
N1
0
0
1
1
Bits [A4:A0] determine which register is accessed during the
data transfer portion of the communication cycle. For multi-
byte transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9878.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock. The serial clock pin is used to synchronize
data transfers from the AD9878 and to run the serial port state
machine. The maximum SCLK frequency is 15 MHz. Input data
to the AD9878 is sampled up on the rising edge of SCLK. Output
data changes upon the falling edge of SCLK.
CS —Chip Select. Active low input starts and gates a commu-
nication cycle. It allows multiple devices to share a common
serial port bus. The SDO and SDIO pins go into a high impedance
state when CS is high. Chip select should stay low during the
entire communication cycle.
SDIO—Serial Data I/O. Data is always written into the AD9878
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 7 of
Register 0x00. The default is Logic 0, which configures the SDIO
pin as unidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9878 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
SCLK
SCLK
SDIO
SDIO
SDO
CS
CS
N0
0
1
0
1
INSTRUCTION BIT 7
t
Figure 19. Timing Diagram for Register Write
Figure 20. Timing Diagram for Register Read
DS
t
DS
DATA BIT N
t
PWH
t
DH
t
Description
Transfer 1 byte
Transfer 2 bytes
Transfer 3 bytes
Transfer 4 bytes
SCLK
t
PWL
INSTRUCTION BIT 6
t
DATA BIT N
DV