AD9878BSTRL Analog Devices Inc, AD9878BSTRL Datasheet - Page 22

• Manufacturer Part Number: AD9878BSTRL
• Description: IC FRONT-END MIXED-SGNL 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9878BSTRL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 4
• Power (watts): 673mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Not Compliant

AD9878
been pulse shaped, there is an additional concern. Typically,
pulse shaping is applied to the baseband data via a filter with a
raised cosine response. In such cases, an α value is used to modify
the bandwidth of the data, where the value of α is such that
A value of 0 causes the data bandwidth to correspond to the
Nyquist bandwidth. A value of 1 causes the data bandwidth to
be extended to twice the Nyquist bandwidth. Thus, with 2× over-
sampling of the baseband data and α = 1, the Nyquist bandwidth
of the data corresponds with the I/Q Nyquist bandwidth. As stated
earlier, this results in problems near the upper edge of the data
bandwidth due to the frequency response of the filters. The
maximum value of α that can be implemented is 0.45, because the
data bandwidth becomes
which puts the data bandwidth at the extreme edge of the flat
portion of the filter response.
If a particular application requires an α value between 0.45 and 1,
the user must oversample the baseband data by at least a factor of
4. Over the frequency range of the data to be transmitted, the
combined HBF 1, HBF 2, and CIC filters introduce a worst-case
droop of less than 0.2 dB.
DIGITAL UPCONVERTER
The digital quadrature modulator stage following the CIC filters
is used to frequency shift (upconvert) the baseband spectrum of
the incoming data stream to the desired carrier frequency. The
carrier frequency is controlled numerically by a direct digital
synthesizer (DDS). The DDS uses the internal system clock
(f
degree of precision. The carrier is applied to the I and Q
multipliers in a quadrature fashion (90° phase offset) and
summed to yield a data stream that is the modulated carrier. The
modulated carrier becomes the 12-bit sample sent to the DAC.
SYSCLK
1
0
) to generate the desired carrier frequency with a high
<
2
–1
–2
–3
–4
–5
–6
(
1
0
α
1
0
+
<
. 1
α
0.1
)
f
NYQ
Figure 25. Cascaded Filter Pass Band
0.2
FREQUENCY RELATIVE TO I/Q NYQ BW
=
. 0
0.3
725
0.4
f
NYQ
0.5
0.6
0.7
0.8
0.9
1.0
Rev. A | Page 22 of 36
Tx SIGNAL LEVEL CONSIDERATIONS
The quadrature modulator itself introduces a maximum gain of
3 dB in signal level. To visualize this, assume that both the I and
Q data are fixed at the maximum possible digital value, x. Then,
the output of the modulator, z, is
It can be shown that |z| assumes a maximum value of
same number of bits represent |z| and x, an overflow occurs.
To prevent this, an effective −3 dB attenuation is internally
implemented on the I and Q data path:
The following example assumes a peak rms level of 10 dB:
The maximum complex input rms value calculation uses both
I and Q symbol components that add a factor of two (6 dB)
to the formula. Table 10 shows typical I-Q input test signals
with amplitude levels related to 12-bit full scale (FS).
Table 10. I-Q Input Test Signals
Analog
Output
Single Tone
(f
Single Tone
(f
Dual Tone
(f
z
C
C
C
− f)
+ f)
± f)
=
z
Maximum
Maximum
z
x
=
2000
±
=
2
[
x
2047
+
1
cos
x
LSBs
2
2
+
LSBs
Digital Input
I = cos(f)
Q = cos(f + 90°)
I = cos(f)
Q = cos(f + 270°)
I = cos(f)
Q = cos(f + 180°)
( )
=
ω
Figure 26. 16-Quadrature Modulation
Symbol
Complex
= −sin(f)
= +sin(f)
FS − 0.2 dBFS
= −cos(f) or
Q = +cos(f)
1
x
t
2
±
−
2
6
=
−
dB
x
0
x
(a gain of +3 dB). However, if the
2 .
sin
Component
−
Input
dB
( )
Peak
ω
X
=
Q
t
±
RMS
]
rms
2000
X
Z
Input Level
FS − 0.2 dB
FS − 0.2 dB
FS − 0.2 dB
FS − 0.2 dB
FS − 0.2 dB
FS − 0.2 dB
Input
Value
( )
dB
I
LSBs
=
Value
=
1265
=
LSBs
Modulator
Output Level
FS − 3.0 dB
FS − 3.0 dB
FS
rms