AD73322LAR Analog Devices Inc, AD73322LAR Datasheet - Page 15

• Manufacturer Part Number: AD73322LAR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)

Figure 15 shows the response of the digital decimation filter
(sinc-cubed response) with nulls every multiple of DMCLK/256
corresponding to the decimation filter update rate for a 64 kHz
sampling. The nulls of the Sinc3 response correspond with
multiples of the chosen sampling frequency. The final detail in
Figure 16 shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented
according to the user’s requirements and available MIPS. The
filtering in Figure 13 through Figure 16 is implemented in the
AD73322L.
Figure 13 to Figure 16 show ADC frequency responses.
DECIMATION FILTER
The digital filter used in the AD73322L carries out two
important functions. First, it removes the out-of-band
quantization noise, which is shaped by the analog modulator
and second, it decimates the high frequency bit stream to a
lower rate, 16-bit word.
F
F
F
F
B
B
B
B
Figure 14. Analog Sigma-Delta Modulator Transfer Function
= 4kHz
= 4kHz
= 4kHz
= 4kHz F
Figure 13. Analog Antialias Filter Transfer Function
Figure 15. Digital Decimator Transfer Function
Figure 16. Final Filter (HPF) Transfer Function
SRNAL
F
SINTER
SIGNAL TRANSFER FUNCTION
= 8kHz
= DMCLK/256
NOISE TRANSFER FUNCTION
F
SINTER
= DMCLK/256
F
F
SINIT
SINIT
= DMCLK/8
= DMCLK/8
Rev. A | Page 15 of 48
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits or
greater (depending on chosen sampling rate). Its Z transform is
given as
where N is set by the sampling rate
Thus, when the sampling rate is 64 kHz, a minimal group delay
of 25 µs can be achieved.
Word growth in the decimator is determined by the sampling
rate. At 64 kHz sampling, where the oversampling ratio (OSR)
between sigma-delta modulator and decimator output equals
32, there are five bits per stage of the three-stage Sinc3 filter.
Due to symmetry within the sigma-delta modulator, the LSB
is always a zero; therefore, the 16-bit ADC output word has
2 LSBs equal to zero, one due to the sigma-delta symmetry and
the other being a padding zero to make up the 16-bit word. At
lower sampling rates, decimator word growth is greater than the
16-bit sample word, therefore truncation occurs in transferring
the decimator output as the ADC word. For example, at 8 kHz
sampling, word growth reaches 24 bits due to the OSR of 256
between the sigma-delta modulator and decimator output. This
yields 8 bits per stage of the three-stage sinc3 filter.
ADC CODING
The ADC coding scheme is in twos complement format, as
shown in Figure 17). The output words are formed by the
decimation filter, which grows the word length from the single
bit output of the sigma-delta modulator to a word length of up
to 24 bits (depending on decimation rate chosen), which is the
final output of the ADC block. In data mode this value is trun-
cated to 16 bits for output on the serial data output (SDO) pin.
[(1 − Z
(N = 32 @ 64 kHz sampling N = 256 @ 8 kHz sampling)
ANALOG
ANALOG
INPUT
INPUT
−N
V
V
)/(1 − Z
V
V
REF
REF
REF
REF
+ (V
– (V
+ (V
– (V
REF
REF
REF
REF
−1
Figure 17. ADC Transfer Function
× 0.32875)
× 0.32875)
)]
× 0.6575)
× 0.6575)
3
V
REF
10...00
10...00
ADC CODE SINGLE-ENDED
ADC CODE DIFFERENTIAL
V
V
V
V
INN
INP
INN
INP
00...00
00...00
AD73322L
01...11
01...11