AD73322LAR Analog Devices Inc, AD73322LAR Datasheet - Page 14

• Manufacturer Part Number: AD73322LAR
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322LAR

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)

AD73322L
FUNCTIONAL DESCRIPTIONS
ENCODER CHANNELS
Both encoder channels consist of a pair of inverting op amps
with feedback connections that can be bypassed if required, a
switched capacitor PGA and a sigma-delta analog-to-digital
converter (ADC). An on-board digital filter, which forms part
of the sigma-delta ADC, also performs critical system-level
filtering. Due to the high level of oversampling, the input
antialias requirements are reduced such that a simple single-
pole RC stage is sufficient to give adequate attenuation in the
band of interest.
PROGRAMMABLE GAIN AMPLIFIER
Each encoder section’s analog front end comprises a switched
capacitor PGA, which also forms part of the sigma-delta
modulator. The SC sampling frequency is DMCLK/8. The
PGA, whose programmable gain settings are shown in Table 8,
may be used to increase the signal level applied to the ADC
from low output sources such as microphones, and can be
used to avoid placing external amplifiers in the circuit. The
input signal level to the sigma-delta modulator should not
exceed the maximum input voltage permitted.
The PGA gain is set by bits IGS0, IGS1, and IGS2 (CRD:0–2) in
control register D.
Table 8. PGA Settings for the Encoder Channel
IGS2
0
0
0
0
1
1
1
1
ADC
Both ADCs consist of an analog sigma-delta modulator and a
digital antialiasing decimation filter. The sigma-delta modulator
noise-shapes the signal and produces 1-bit samples at a
DMCLK/8 rate. This bit stream, representing the analog input
signal, is input to the antialiasing decimation filter. The
decimation filter reduces the sample rate and increases the
resolution.
ANALOG SIGMA-DELTA MODULATOR
The AD73322L’s input channels employ a sigma-delta
conversion technique, which provides a high resolution 16-bit
output with system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as
oversampling, where the sampling rate is many times the
IGS1
0
0
1
1
0
0
1
1
IGS0
0
1
0
1
0
1
0
1
Gain (dB)
0
6
12
18
20
26
32
38
Rev. A | Page 14 of 48
highest frequency of interest. In the case of the AD73322L, the
initial sampling rate of the sigma-delta modulator is DMCLK/8.
The main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to F
(Figure 13). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 14). The combin-
ation of these techniques, followed by the application of a
digital filter, sufficiently reduces the noise in band to ensure
good dynamic performance from the part (Figure 15).
Figure 13 through Figure 16 show the various stages of filtering
that are employed in a typical AD73322L application. Figure 13
shows the transfer function of the external analog antialias
filter. Even though it is a single RC pole, its cutoff frequency
is sufficiently far away from the initial sampling frequency
(DMCLK/8) that it takes care of any signals that could be
aliased by the sampling frequency. This also shows the major
difference between the initial oversampling rate and the band-
width of interest. In Figure 14, the signal and noise-shaping
responses of the sigma-delta modulator are shown. The
signal response provides further rejection of any high
frequency signals, while the noise-shaping pushes the inherent
quantization noise to an out-of-band position. The detail of
INTEREST
INTEREST
INTEREST
BAND
BAND
BAND
OF
OF
OF
Figure 12. Sigma-Delta Noise Reduction
NOISE SHAPING
DIGITAL FILTER
A.
B.
C.
S
/2 = DMCLK/16
DMCLK/16
DMCLK/16
DMCLK/16
F
F
F
S
S
S
/2
/2
/2