MAXQ3181-RAN+ Maxim Integrated Products, MAXQ3181-RAN+ Datasheet
MAXQ3181-RAN+
Specifications of MAXQ3181-RAN+
Related parts for MAXQ3181-RAN+
MAXQ3181-RAN+ Summary of contents
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... Active Energy Electricity Meters Ordering Information PART TEMP RANGE MAXQ3181-RAN+ -40°C to +85°C + Denotes a lead(Pb)-free/RoHS-compliant package. Pin Configuration and Typical Application Circuit appear at end of data sheet. MAXQ is a registered trademark of Maxim Integrated Products, Inc. ...
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Low-Power, Active Energy, Polyphase AFE Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Low-Power, Active Energy, Polyphase AFE TABLE OF CONTENTS (continued) Global Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Low-Power, Active Energy, Polyphase AFE TABLE OF CONTENTS (continued) Virtual Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Low-Power, Active Energy, Polyphase AFE TABLE OF CONTENTS (continued) Calibration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Calibration Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Calibrating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Calibrating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Calibrating Phase Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Interfacing the MAXQ3181 to External Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Connections to the Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Sensor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Voltage Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Voltage-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Voltage Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Current Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Current Shunt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Current Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Advanced Operation ...
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... Real Energy, Phase X = A/B/C (X.ACT) (A: 0x1D0, B: 0x2BC, C: 0x3A8 .79 Apparent Energy, Phase X = A/B/C (X.APP) (A: 0x1D8, B: 0x2C4, C: 0x3B0 .79 Checksum (CHKSUM) (0x060 .80 Neutral Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 RMS Current, Neutral (I.N) (0x840 .81 Special Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Specific Design Considerations for MAXQ3181-Based Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 6 _______________________________________________________________________________________ ...
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... Figure 4a. SPI Interface Timing (CKPHA = .18 Figure 4b. SPI Interface Timing (CKPHA = .18 Figure 5. Read SPI Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 6. Write SPI Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 7. Flowchart for Reading from MAXQ3181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 8. Flowchart for Writing to MAXQ3181 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Figure 9. Per Sample Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Figure 10. Computation of RMS Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Figure 11. Phase Compensation for Energy Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Figure 12 ...
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Low-Power, Active Energy, Polyphase AFE ABSOLUTE MAXIMUM RATINGS Voltage Range on DVDD Relative to DGND .........-0.3V to +4.0V Voltage Range on AVDD Relative to AGND..........-0.3V to +4.0V Voltage Range on AGND Relative to DGND .........-0.3V to +0.3V Voltage Range on ...
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Low-Power, Active Energy, Polyphase AFE ELECTRICAL CHARACTERISTICS (continued 3.6V -40°C to +85°C, unless otherwise noted.) (Note 2) AVDD DVDD RST A PARAMETER SYMBOL Input Low Current RESET Pullup Resistance R Output High ...
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Low-Power, Active Energy, Polyphase AFE ELECTRICAL CHARACTERISTICS (continued 3.6V -40°C to +85°C, unless otherwise noted.) (Note 2) AVDD DVDD RST A PARAMETER SYMBOL SSEL Low to First SCLK Edge (Slave Enable) Last ...
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... HW MULTIPLY 48-BIT ACCUMULATE ______________________________________________________________________________________ REF ADC ADC CONTROL, ELECTRICITY METERING DSP, COMMUNICATIONS MANAGER WATCHDOG TIMER POR/ BROWNOUT SYSCLK MONITOR ADCCLK MAXQ3181 Block Diagram CFP, CFQ COUNTERS I/O BUFFERS I/O REGISTERS SPI I/O BUFFERS I/O REGISTERS I/O I/O REGISTERS BUFFERS HF RC OSC/8 ...
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... Master Out-Slave In Input. This line is used by the master to transmit data to the slave (the 15 MOSI MAXQ3181) over the SPI interface. Master In-Slave Out Output. This line is used by the MAXQ3181 (the slave) to transmit data back to 16 MISO the master over the SPI interface. ...
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... Precision Pulse Generators The MAXQ3181 includes a precision pulse generator that generates a pulse whenever certain conditions are met. In the MAXQ3181, many meter quantities can be selected for conversion to meter pulses including absolute energy, net energy, voltage, and current. The pulse generator is an accumulator. On each DSP cycle, whatever quantity is being measured— ...
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... INTERNAL RESET Figure 1. External Reset 14 ______________________________________________________________________________________ MAXQ3181, the SSEL line is normally driven low at the beginning of each SPI command. This means that if the master sends an SPI command after the MAXQ3181 enters Stop Mode, the MAXQ3181 automatically exits Stop Mode. There are several different sources that can cause the MAXQ3181 to undergo a reset cycle ...
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... Under normal circumstances, the MAXQ3181 always resets the watchdog timer often Power-On Reset enough to prevent it from expiring. However inter- nal error of some kind causes the MAXQ3181 to lock up power-fail RST or enter an endless execution loop, the watchdog timer expires and triggers an automatic hardware reset. ...
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... PWRF has been set hardware, it can only be cleared by the master ( system reset). Whenever PWRF = 1, if the EPWRF interrupt masking bit is also set to 1, the MAXQ3181 drives IRQ low to signal to the master that an interrupt condition (in this case, a power- fail warning) exists and requires attention. ...
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... SPI bus interface, is also used for master/slave communications because it allows the MAXQ3181 to notify the master that an interrupt condi- tion exists. Some SPI peripherals sacrifice speed in favor of simulating a half-duplex operation. This is not the case with the MAXQ3181 truly a full-duplex SPI slave. 17 ...
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... Transfers over the SPI interface always start with the most significant bit and end with the least significant bit. All SPI data transfers to and from the MAXQ3181 are always 8 bits (one byte) in length. The MAXQ3181 SPI interface does not support 16-bit character lengths. ...
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... MAXQ3181’s clock frequency divided by 4. For example, when the MAXQ3181 is run- ning at 8MHz, the SPI clock frequency must be 2MHz or less. And if the MAXQ3181 is running in LOWPM Mode (or if the crystal is still warming up), the SPI clock frequency must remain at 250kHz or less for proper communications operation ...
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... For this reason, the MAXQ3181 always sends zero or more bytes of a NAK character (0x4E or ASCII ‘N’) followed by an ACK char- acter (0x41, or ASCII ‘A’) before sending the data. ...
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... The 8-bit CRC is calculated for all bytes in a transaction, from the first command byte sent by the master through the last data byte excluding sync bytes, using the polynomial mitted CRC byte does not match the calculated CRC byte (for a write command), the MAXQ3181 ignores the command. ... 8 5 ...
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... This byte spacing must be no less than 400 system clocks to ensure that the MAXQ3181 has a chance to read and process the byte before the arrival of the next one strongly rec- ommended that CRC be enabled for both read and write to achieve reliable communications ...
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... They are calculated at the time they are requested, and thus can involve addi- ______________________________________________________________________________________ DONE? EXIT Figure 8. Flowchart for Writing to MAXQ3181 tional time to return a value. Most virtual registers are 8 bytes in length and are delivered least significant byte first. WRITE MAXQ3181 ...
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Low-Power, Active Energy, Polyphase AFE Table 3. RAM Register Map x0h x1h x2h x3h 0x00 STATUS MODE1 MODE2 MODE3 0x01 AUX_CFG SYS_KHZ 0x02 PLS1_WD THR1 0x03 AVG_C HPF_C 0x04 NS R_ 0x05 R_ADCACQ SPICF 0x06 CHKSUM LINEFR ...
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Low-Power, Active Energy, Polyphase AFE Table 4. Virtual Register Map x0 x1 0x80 PWRP.A 0x81 0x82 PWRS.A 0x83 V.A 0x84 I.N I.A 0x85 0x86 0x87 ENRS.A 0x88 0x89 0x8A 0x8B 0x8C ENRP.A 0x8D 0x8E 0x8F 0xC0 DSPVER RAWTEMP Note: All ...
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... BIT NAME — Reserved. When set, the high-frequency crystal has failed and the MAXQ3181 is operating from its internal ring 6 CROFF oscillator. Under these circumstances, energy accumulation is not accurate and the SPI bus does not operate at full speed. When set, the last reset was due to power-on-reset. Host should clear this bit to allow the next POR ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: — — Reset BIT NAME 7:5, 0 — Reserved. When set, the high-frequency crystal oscillator is disabled and the XTAL1 pin is configured EXTCLK clock ...
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... ______________________________________________________________________________________ Operating Mode Register 1 (OPMODE1) (0x002) (continued) FUNCTION Use this configuration when the load is connected in a wye arrangement and neutral is connected to MAXQ3181 ground, or when the load is connected in a delta arrangement and isolated voltage and current sensors are used. This C arrangement measures power in each load branch rather than power in each source branch ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: — — Reset BIT NAME 7:4 — Reserved. Selects the current linearity offset calibration method. See the Calibrating Current Offset section for more information. 3 LINFRM 2 + OFFS ...
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Low-Power, Active Energy, Polyphase AFE BIT NAME 3V3A (10) 2:1 WIRSYS 1P3W (00) Selects the mechanism to use for calculating apparent power. 0 APPSEL RMS 30 ______________________________________________________________________________________ Operating Mode Register 2 (OPMODE2) (0x003) (continued) ...
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... When set, the direction of real energy flow has changed (that is, from toward the load to away from the 12 DCHA load, or from away from the load to toward the load). When set, the MAXQ3181 has failed to detect zero crossings on one or more voltage channels for the 11 NOZX time defined by the NZX_TIMO register. ...
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... EDCHA been observed to have changed (that is, from toward the load to away from the load, or from away from the load to toward the load). When set, this flag causes the IRQ pin to become active when the MAXQ3181 has failed to detect zero 11 ENOZX crossings on one or more voltage channels for at least one DSP cycle. ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: This register selects which phases are included in the CFP pulse output and also selects which quantity is accumu- lated to drive the pulse output. BIT NAME CFP Pulse Output ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: Bit Name: Reset: Bit Name: Reset: This register designates the threshold of the CFP pulse. This value is used to set ...
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Low-Power, Active Energy, Polyphase AFE Voltage Gain, Phase X = A/B/C (X.V_GAIN) (A: 0x132, B: 0x21E, C: 0x30A) Bit Name: Reset: Bit Name: Reset: This register contains gain coefficient for phase X voltage channel. The raw ...
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Low-Power, Active Energy, Polyphase AFE Phase-Angle Compensation, Medium Range, Phase X = A/B/C (X.PA1) Bit Name: Reset: Bit Name: Reset: This signed register contains the angle fraction of one radian, to add to the ...
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... Name: Reset: This register specifies the fraction of full-scale current below which a no-load condition is declared. When X.IRMS falls below this level, the MAXQ3181 no longer accumulates power for phase X. Full scale is represented by 0x10000. The maximum value for this register is 0xFFFF. ______________________________________________________________________________________ Overvoltage Level (OVLVL) (0x046) ...
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Low-Power, Active Energy, Polyphase AFE Interrupt Flags, Phase X = A/B/C (X.FLAGS) (A: 0x144, B: 0x230, C: 0x31C) Bit Name: — — Reset The X.FLAGS register contains condition flags that relate to the function of phase ...
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Low-Power, Active Energy, Polyphase AFE Interrupt Mask, Phase X = A/B/C (X.MASK) (A: 0x145, B: 0x231, C: 0x31D) Bit Name: — DIR_A Reset BIT NAME 7, 5 — Reserved. Active Energy Direction Status 6 DIR_A 0 ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: Line frequency, LSB = 0.001Hz. Power Factor, Phase X = A/B/C (X.PF) (A: 0x1C6, B: 0x2B2, C: 0x39E) Bit Name: Reset: Bit: 7 ...
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Low-Power, Active Energy, Polyphase AFE RMS Current, Phase X = A/B/C (X.IRMS) (A: 0x1CC, B: 0x2B8, C: 0x3A4) Bit Name: Bit Name: Bit Name: Bit Name: This register provides the raw RMS ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Bit Name: Bit Name: Bit Name: On every DSP cycle, the contents of the X.ACT register are tested, and, if negative, absolute values are added ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: This register contains the value by which the raw voltage value in each phase (A.VRMS, B.VRMS, and C.VRMS) is multiplied before being presented to the ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: This register contains the value by which the raw power value in each phase is multiplied before being presented to the virtual power registers. The ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: This register contains the value by which the raw accumulated energy value in each phase is multiplied before being presented to the virtual energy registers. ...
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Low-Power, Active Energy, Polyphase AFE The virtual registers are calculated values derived from one or more real registers. They are calculated at the time they are requested, and thus could involve additional time to return a value. Most virtual registers ...
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Low-Power, Active Energy, Polyphase AFE RMS Volts, Phase X = A/B/C (V.X) (A: 0x831, B: 0x832, C: 0x834) This register contains the RMS voltage on phase A/B/C. The units are defined by the VOLT_CC setting such that V.X = X.VRMS ...
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Low-Power, Active Energy, Polyphase AFE Real Energy, Phase A/B/C/T (ENRP.X) (A: 0x8C1, B: 0x8C2, C: 0x8C4, T: 0x8C7) This signed register contains the real accumulated energy delivered into phase A/B/C or total. The register is calcu- lated according to the ...
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... Low-Power, Active Energy, Polyphase AFE Theory of Operation Analog Front-End Operation Whenever the MAXQ3181 is in one of the active operat- ing modes (Run Mode or LOWPM Mode), the analog front-end operates continuously, scanning up to eight scan slots depending on the selected front-end config- uration. For each analog scan slot that is enabled, one of the eight differential input pairs is measured ...
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... A better method is to use each newly cal- culated value input to a filter. The output of the filter is then the value of NS that is actually used in calculations. In the MAXQ3181, this filter is controlled by the AVG_NS register. A second problem with updating NS on every line cycles is the fact that noise impulses that occur at near- ...
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... Consequently, for the most precise measurements, the phase between the voltage and current signals must be compensated. In the MAXQ3181, the energy signals are compensated for phase offset by performing a complex multiplication of the signal with the contents of the appropriate phase offset register ...
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... If the NOZXM bit is set, this flag sets the NOZX bit in the IRQ_FLAG. If the inter- rupt enable bit ENOZX is set to 1, the interrupt signal IRQ is driven low by the MAXQ3181 whenever NOZX = 1. The master can clear NOZXF and NOZX back remove the interrupt condition. ...
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... Full scale is represented by 0x10000. So far in this discussion, the values being calculated and managed in the MAXQ3181 have been based on fundamental units meaningful to the device itself: volt- age as a binary fraction of full-scale voltage; current as a binary fraction of full-scale current, and time as a non- integer multiple of the ADC frame time ...
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... The MAXQ3181 measures energy. But power is just energy per unit time, and the MAXQ3181 keeps track of the time unit over which energy is accumulated. This is simply the NS value, the fractional number of samples that comprises one DSP cycle. So converting energy to power is as simple as dividing the accumulated energy over one DSP cycle by NS ...
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... PHASEA, PHASEB, and PHASEC bits in the PLSCFG1 register to include them in the accumulation. Generating Pulses On every DSP cycle, the MAXQ3181 adds the value in the selected register (or set of registers) to the pulse accumulator. If the value in the pulse accumulator exceeds the value in the associated threshold register ...
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... MAXQ3181 detects the RMS-value exceeding a thresh- old level, the interrupt flag is set. If enabled, any of these flags issues an interrupt request. All inter- rupt flags are “sticky” bits—the MAXQ3181 never clears them on its own unless a reset occurs. The inter- rupt flags should be cleared by the master by writing the appropriate register ...
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... Low-Power, Active Energy, Polyphase AFE When reading virtual registers, the MAXQ3181 uses the configurable conversion coefficients AMP_CC, Table 5. Meter Unit Definitions REGISTER OR ACCUMULATOR Current RMS: X.IRMS Pulse output current RMS THR1, when pulse output configured to IRMS Voltage RMS: X.VRMS Pulse output RMS voltage THR1, when pulse output configured to VRMS Energy: X ...
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... I Use the default ADC timing t = 320μs, we get the fol- FR lowing meter unit to physical unit conversion coeffi- cients (these coefficients are not part of the MAXQ3181 registers): 24 MU_AMP = 6.1E-6 (A) FS ...
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... FS • Divide the applied value (in meter unit) by the value read from the MAXQ3181. The result should be a value between 0 and 2. If the value falls outside of this range, you have probably miscalculated V • Multiply the calculated value by 2 gain value to be programmed into A.V_GAIN. Ensure the most significant bit is 0 ...
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... Low-Power, Active Energy, Polyphase AFE • Divide the applied value (in meter unit) by the value read from the MAXQ3181. The result should be a value between 0 and 2. If the value falls outside of this range, you have probably miscalculated I • Multiply the calculated value by 2 gain value to be programmed into A ...
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... When selecting resistors for a voltage-divider, keep the division ratio high enough so that the peak voltage value cannot exceed the maximum allowable input voltage. In the MAXQ3181, the peak input voltage is about 1V; consequently, a divider in the range of 400:1 to 600:1 is ideal. The second consideration is the total power dissipation and voltage hold-off requirements of the resistor tempting to design a 400:1 divider with a 400kΩ ...
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... ZC_LPF register. This register specifies the b ficient of a first-order LPF using following formula: The MSB of this register must be zero. For each phase A, B, and C, the MAXQ3181 counts the number of scan frames (NS) between zero crossings within a DSP cycle. Each individual phase ...
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... The current offset (X.OFFS_HI A/B/C) can be used to compensate the current channel nonlinearity. Since the MAXQ3181 tracks the input current to deter- mine what linearity compensation factors to use, the user must choose two points (i above the low current threshold, and get the X.IRMS ...
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... I . Divide the results of this cal- FS culation by the value read from the MAXQ3181. The result should be a value between 0 and 2. Convert the 14 integer by multiplying 2 , and ensure MSB is zero. The result is the gain value to be programmed into A ...
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... These registers configure the time slot normally assigned to current channels A/B/C. We recommend leaving these registers at their default values. If they must be reassigned, one must ensure that all the current and voltage chan- nels are reassigned properly so that the MAXQ3181 computes the power/energy parameters as intended by your setup. ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset A: Reset B: Reset C: These registers configure the time slot normally assigned to voltage channels A/B/C. The user may wish to change the PGG settings to match the voltage ...
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Low-Power, Active Energy, Polyphase AFE Time Slot Assignment—Neutral Current Channel (SCAN_IN) (0x00E) Bit Name: Reset: This register configures the time slot normally assigned to the neutral current channel. The user can change the DADCNV bit to enable/disable neutral ...
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Low-Power, Active Energy, Polyphase AFE Time Slot Assignment—Temperature Channel (SCAN_TE) (0x00F) Bit Name: Reset: This register configures the time slot normally assigned to the temperature measurement device. This register is managed by the firmware and should not be ...
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... Name: — ENAUX Reset The MAXQ3181 can monitor the RMS value of one auxiliary channel in addition to its normal processing. The Auxiliary Channel Configuration register selects which input the auxiliary channel processes and what processing is applied to the auxiliary channel. BIT NAME 15:7 — ...
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... The NS register defines the fundamental timing for the electricity meter. It defines a DSP cycle in terms the period of the ADC scan frame. Generally, this register is calculated and updated automatically by the MAXQ3181 firmware based on the zero-crossing detection, and whether noise rejection (REJ_NS) and averaging (AVG_NS) are enabled. ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: This register establishes the sensitivity of the NS rejection filter setting measure of the line frequency line cycle occurs that ...
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Low-Power, Active Energy, Polyphase AFE Bit Name: Reset: Bit Name: Reset: This register determines whether the all other measured values in the electricity meter are averaged over time. If the value of this register is nonzero, ...
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... ADCASD ADCRY Reset This register is a mirror of a CPU register in the MAXQ3181. This register should not be modified by supervisory code. BIT NAME Disable ADC Automatic Shutdown. Normally, the ADC analog section is powered off following a conversion to conserve power. If this bit is set, the ADC leaves the analog section powered on ...
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... Name: ESPII SAS Reset This register is a mirror of a CPU register in the MAXQ3181. This register configures the SPI port of the MAXQ3181. BIT NAME 7 ESPII Enable SPI Interrupt. If set, arrival of a character on the SPI bus causes a CPU interrupt. SPI Slave Select Polarity. If clear, SSEL is assumed to be active low; if set, SSEL is assumed to be ...
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... Name: Reset: This register specifies the time in DSP cycles that the MAXQ3181 waits before accumulating energy. If this register is nonzero decremented on each DSP cycle. If the result of the decrement is nonzero, the results of the DSP cycle are discarded and are not accumulated to the energy registers. This register is useful for delaying the initiation of energy accumulation on startup or after some hardware function has been modified ...
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... Reset: Bit Name: Reset: This register specifies the fraction of full-scale current that causes the MAXQ3181 to switch from PA1 to PA2 to pro- vide phase-angle compensation. For more information, see the PA0, PA1, and PA2 register descriptions. The full- scale current is represented by 0x10000. Bit ...
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Low-Power, Active Energy, Polyphase AFE Linearity Offset, High Range, Phase X = A/B/C (X.OFFS_HI) (A: 0x138, B: 0x224, C: 0x310) Bit Name: Reset: Bit Name: Reset: This signed register contains the linearity offset for phase X ...
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Low-Power, Active Energy, Polyphase AFE Linearity Offset, Low Range, Phase X = A/B/C (X.OFFS_LO) (A: 0x13C, B: 0x228, C: 0x314) Bit Name: Reset: Bit Name: Reset: This signed register contains the linearity offset for phase X ...
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Low-Power, Active Energy, Polyphase AFE Real Energy, Phase X = A/B/C (X.ACT) (A: 0x1D0, B: 0x2BC, C: 0x3A8) Bit Name: Bit Name: Bit Name: Bit Name: This signed register provides the raw ...
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... This register contains the calculated 16-bit arithmetic checksum over critical configuration and calibration registers updated on every DSP cycle. In use, the administrative processor records the value in the CHKSUM register and then checks it periodically to verify that no configuration or calibration registers have changed. The MAXQ3181 sets the CHSCH bit when this register’s value changes. ...
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... Doing so reduces the susceptibility of the design to fast transient noise. Because the MAXQ3181 is designed for use in systems where high voltages are present, care must be taken to route all signal paths, both analog and digital, as far away as possible from the high-voltage components ...
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... Low-Power, Active Energy, Polyphase AFE the MAXQ3181 devices together but using separate slave select lines to individually select each MAXQ3181. Additional Documentation Designers must ensure they have the latest MAXQ3181 errata documents. Errata sheets contain deviations from published specifications. A MAXQ3181 errata sheet for any specific device revision is available at www ...
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... Low-Power, Active Energy, Polyphase AFE VOLTAGE SENSE CURRENT TRANSFORMER ______________________________________________________________________________________ Typical Application Circuit R1 V0P R2 R1 V1P R2 MAXQ3181 R1 V2P R2 VCOMM VN I0P R3 R3 I0N I1P R3 R3 I1N I2P R3 R3 I2N MASTER 83 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 84 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products ...