AD7195BCPZ Analog Devices Inc, AD7195BCPZ Datasheet
AD7195BCPZ
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AD7195BCPZ Summary of contents
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FEATURES sensor excitation RMS noise: 8 4.7 Hz (gain = 128) 16 noise-free bits at 2.4 kHz (gain = 128 22.5 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ...
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AD7195 TABLE OF CONTENTS Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...
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SPECIFICATIONS 5.25 V, AGND = DGND = 0 V; REFIN(+) = unless otherwise noted. A MIN MAX Table 1. ...
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AD7195 Parameter Min External Clock @ 50 Hz 100 ANALOG INPUTS Differential Input Voltage Ranges −(AV − DD 1.25 V)/gain 2 Absolute AIN Voltage Limits Unbuffered Mode AGND − ...
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Parameter Min LOGIC INPUTS 2 Input High Voltage INH 2 Input Low Voltage, V INL 2 Hysteresis 0.1 Input Currents −10 LOGIC OUTPUT (DOUT/ RDY ) 2 Output High Voltage − 0 Output ...
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AD7195 TIMING CHARACTERISTICS 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic otherwise noted. Table 2. ...
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Circuit and Timing Diagram DOUT/RDY (O) SCLK (I) SCLK (I) I (1.6mA WITH DV SINK 100µA WITH OUTPUT 1.6V PIN 50pF I (200µA WITH DV SOURCE 100µA WITH DV DD Figure 2. Load Circuit for Timing Characterization ...
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AD7195 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating AV to AGND −0 +6 AGND −0 +6 AGND to DGND −0 +0.3 ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1 ACX2 Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications ...
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AD7195 Pin No. Mnemonic Description 20 BPDSW Bridge Power-Down Switch to AGND. 21 AGND Analog Ground Reference Point. 22 DGND Digital Ground Reference Point Analog Supply Voltage Digital Supply ...
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TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,748 8,388,746 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, Gain = 128, REF 4 Chop Disabled, Sinc Filter) 250 200 ...
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AD7195 3.0 2.0 1.0 0 –1.0 –2.0 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 V (V) IN Figure 12. INL (Gain = –2 –4 –6 –0.020 –0.015 –0.010 –0.005 0 0.005 V (V) IN ...
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RMS NOISE AND RESOLUTION The tables in this section show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolu- tion of the AD7195 for various output data rates and gain settings, with chop disabled and chop enabled for ...
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AD7195 3 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 4.7 639.4 640 7.5 400 480 10 300 ...
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SINC CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 1.175 1702 640 1.875 1067 480 2.5 800 96 12.5 160 80 15 133 ...
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AD7195 3 SINC CHOP ENABLED Table 15. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 1.56 1282 640 2.5 800 480 3.33 600 96 16.6 120 80 20 ...
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ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions, the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise ...
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AD7195 COMMUNICATIONS REGISTER (RS2, RS1, RS0 = The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register ...
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STATUS REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be ...
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AD7195 Table 22. Mode Register Bit Designations Bit Location Bit Name Description MR23 to MR21 MD2 to MD0 Mode select bits. These bits select the operating mode of the AD7195 (see Table 23). MR20 DAT_STA This bit enables the transmission ...
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Table 23. Operating Modes MD2 MD1 MD0 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in ...
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AD7195 Table 24. Configuration Register Bit Designations Bit Location Bit Name Description CON23 CHOP Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the ...
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Table 25. Channel Selection Channel Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 CH3 DATA REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x000000) The conversion result from the ADC is ...
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AD7195 OFFSET REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x800000) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7195 has four offset registers; ...
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ADC CIRCUIT INFORMATION AIN1 AIN2 AIN3 AIN4 AINCOM BPDSW OVERVIEW The AD7195 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals, such as ...
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AD7195 ANALOG INPUT CHANNEL The AD7195 has two differential/four pseudo differential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a ...
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ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is ...
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AD7195 in ac excitation where resistor divider arrangements on the reference input add to the settling time associated with the switching. When the ACX bit in the configuration register is set to 0, the digital outputs ACX1 and ACX2 are ...
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The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/ RDY lines are used to communicate with the AD7195. The end of the conversion can be monitored using the RDY ...
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AD7195 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7195 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also ...
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Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7195 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to ...
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AD7195 RESET The circuitry and serial interface of the AD7195 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, ...
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BRIDGE POWER-DOWN SWITCH In bridge applications, such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350 Ω load cell requires current when excited with ...
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AD7195 DIGITAL FILTER The AD7195 offers a lot of flexibility in the digital filter. The device has four filter options. The device can be operated 3 4 with a sinc or sinc filter, chop can be enabled or disabled, and ...
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When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ...
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AD7195 The output data rate when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 31 shows the 4 frequency response of the sinc filter. The filter provides 50 Hz ±1 Hz and ...
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The output data rate equals /(3 × 1024 × FS[9:0]) ADC SETTLE CLK where the output data rate. ADC f is the master clock (4.92 MHz nominal). CLK FS[9:0] is the decimal equivalent ...
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AD7195 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 38. The output data rate when zero latency is disabled and 3.3 ...
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When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/f . ADC CHANNEL A CHANNEL CONVERSIONS CH ...
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AD7195 3 CHOP ENABLED (SINC FILTER) With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter ...
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The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 49 is achieved. The output ...
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AD7195 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are common- mode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog ...
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APPLICATIONS INFORMATION The AD7195 provides a low-cost, high resolution analog-to- digital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial ...
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... ORDERING GUIDE 1 Model Temperature Range AD7195BCPZ –40°C to +105°C AD7195BCPZ-RL –40°C to +105°C AD7195BCPZ-RL7 –40°C to +105° RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.10 0.30 5 ...