AD73360AR-REEL7 Analog Devices Inc, AD73360AR-REEL7 Datasheet - Page 6

• Manufacturer Part Number: AD73360AR-REEL7
• Description: IC ANALOG FRONT END 6CH 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73360AR-REEL7

• Number Of Channels: 6
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Power (watts): 80mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 28-SOIC (7.5mm Width)
• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Serial (6-Wire)
• Sample Rate: 64KSPS
• Input Voltage Range: 1.64375V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Resolution: 16b
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC W
• For Use With: EVAL-AD73360LEB - BOARD EVAL FOR AD73360L
• Lead Free Status / RoHS Status: Not Compliant

AD73360
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
TIMING CHARACTERISTICS
Parameter
Clock Signals
Serial Port
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
5
6
7
8
9
10
11
12
13
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
Limit at
T
61
24.4
24.4
t
0.4 × t
0.4 × t
20
0
10
10
10
10
30
1
1
A
A
= –40 C to +85 C
= –40 C to +85 C
1
1
1
1
(AVDD = 5 V
noted)
(AVDD = 3 V
noted)
10%; DVDD = 5 V
10%; DVDD = 3 V
–6–
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
10%; AGND = DGND = 0 V; T
10%; AGND = DGND = 0 V; T
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
A
A
= T
= T
MlN
MlN
to T
to T
MAX
MAX
, unless otherwise
, unless otherwise
REV. A