AD73360AR-REEL7 Analog Devices Inc, AD73360AR-REEL7 Datasheet - Page 23

• Manufacturer Part Number: AD73360AR-REEL7
• Description: IC ANALOG FRONT END 6CH 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73360AR-REEL7

• Number Of Channels: 6
• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Power (watts): 80mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 28-SOIC (7.5mm Width)
• Analog Front End Type: General Purpose
• Analog Front End Category: General Purpose
• Interface Type: Serial (6-Wire)
• Sample Rate: 64KSPS
• Input Voltage Range: 1.64375V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Resolution: 16b
• Number Of Adc's: 6
• Power Supply Type: Analog/Digital
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC W
• For Use With: EVAL-AD73360LEB - BOARD EVAL FOR AD73360L
• Lead Free Status / RoHS Status: Not Compliant

REV. A
Cascade Operation
The AD73360 has been designed to support up to eight devices
in a cascade connected to a single serial port (see Figure 17).
The SPORT interface protocol has been designed so that device
addressing is built into the packet of information sent to the
device. This allows the cascade to be formed with no extra hard-
ware overhead for control signals or addressing. A cascade can
be formed in either of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate, serial clock and number of
devices can be successfully cascaded. This assumes a directly
coupled frame sync arrangement as shown in Figure 12 and does
not take any interrupt latency into account.
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
FL0
ADSP-2181
Figure 17. Connection of Two AD73360s Cascaded to
ADSP-2181
DSP
FL1
f
D0
D1
1
S
≥
RFS
TFS
DT
SCLK
DR
6
74HC74
×
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6
[((
CLK
Device Count
Q0
Q1
DEVICE 2 - CHANNEL 1
SDIFS
SDIFS
SDOFS
SDOFS
SCLK
SCLK
SDO
SDI
SDO
SDI
SCLK
Figure 18. Cascade Timing for a Two-Device Cascade
−
AD73360
AD73360
DEVICE 1
DEVICE 2
1
)
×
16
)
+
17
RESET
MCLK
RESET
MCLK
SE
SE
]
–23–
DEVICE 1 - CHANNEL 1
In Cascade Mode, each device must know the number of de-
vices in the cascade to be able to output data at the correct
time. Control Register A contains a 3-bit field (DC0–2) that is
programmed by the DSP during the programming phase. The
default condition is that the field contains 000b, which is equiva-
lent to a single device in cascade (see Table XVIII). However,
for cascade operation this field must contain a binary value that
is one less than the number of devices in the cascade. With a
number of AD73360s in cascade each device takes a turn to
send an ADC result to the DSP. For example, in a cascade of
two devices the data will be output as Device 2-Channel 1,
Device 1-Channel 1, Device 2-Channel 2, Device 1-Channel 2
etc. When the first device in the cascade has transmitted its
channel data there is an additional SCLK period during which
the last device asserts its SDOFS as it begins its transmission of
the next channel. This will not cause a problem for most DSPs
as they count clock edges after a frame sync and hence the
extra bit will be ignored.
When multiple devices are connected in cascade there are also
restrictions concerning which ADC channels can be powered
up. In all cases the cascaded devices must all have the same
channels powered up (i.e., for a cascade of two devices requir-
ing Channels 1 and 2 on Device 1 and Channel 5 on Device 2,
Channels 1, 2 and 5 must be powered up on both devices to
ensure correct operation). Figure 18 shows the timing se-
quence for two devices in cascade.
DC2
0
0
0
0
1
1
1
1
Connection of a cascade of devices to a DSP, as shown in
Figure 17, is no more complicated than connecting a single
device. Instead of connecting the SDO and SDOFS to the
DSP’s Rx port, these are now daisy-chained to the SDI and
SDIFS of the next device in the cascade. The SDO and
SDOFS of the final device in the cascade are connected to the
DSP’s Rx port to complete the cascade. SE and RESET on all
devices are fed from the signals that were synchronized with
the MCLK using the circuit of Figure 19. The SCLK from
only one device need be connected to the DSP’s SCLK input(s)
as all devices will be running at the same SCLK frequency and
phase.
7 8 9 10 11 12 13 14 15 16 17
Table XVIII. Device Count Settings
DC1
0
0
1
1
0
0
1
1
1 2 3 4 5 6 7
DEVICE 2 - CHANNEL 2
DC0
0
1
0
1
0
1
0
1
8
AD73360
Cascade Length
1
2
3
4
5
6
7
8