M41T81MX6 STMicroelectronics, M41T81MX6 Datasheet - Page 7

• Manufacturer Part Number: M41T81MX6
• Description: IC RTC SERIAL W/ALARM 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T81MX6

• Memory Size: 20B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2822-5

M41T81
2
2.1
2.1.1
Operation
The M41T81 clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
●
●
●
●
●
●
●
●
●
●
●
●
●
The M41T81 clock continually monitors V
fall below V
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. The device also
automatically switches over to the battery and powers down into an ultra low current mode
of operation to conserve battery life. As system power returns and V
battery is disconnected, and the power supply is switched to external V
For more information on battery storage life refer to application note AN1012.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
Accordingly, the following bus conditions have been defined:
Bus not busy
Both data and clock lines remain high.
1
2
3
4
5
6
7
8
9
10
11
17
20
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
st
nd
rd
th
th
th
th
th
th
th
th
th
th
byte: tenths/hundredths of a second register
byte: century/hours register
byte: day register
byte: date register
byte: month register
byte: year register
byte: control register
byte: minutes register
byte: seconds register
byte: watchdog register
- 16
- 19
byte: square wave register
SO
th
th
, the device terminates an access in progress and resets the device address
bytes: alarm registers
bytes: reserved
Doc ID 7529 Rev 10
CC
for an out-of-tolerance condition. Should V
CC
rises above V
CC
.
Operation
SO
, the
CC
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