M41T81MX6 STMicroelectronics, M41T81MX6 Datasheet - Page 11

• Manufacturer Part Number: M41T81MX6
• Description: IC RTC SERIAL W/ALARM 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T81MX6

• Memory Size: 20B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2822-5

M41T81
2.3
2.4
Figure 9.
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
WRITE mode
In this mode the master transmitter transmits to the M41T81 slave receiver. Bus protocol is
shown in
(R/W=0) is placed on the bus and indicates to the addressed device that word address “An”
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T81 slave receiver will
send an acknowledge clock to the master transmitter after it has received the slave address
see
byte.
Data retention mode
With valid V
WRITE Cycles. Should the supply voltage decay, the power input will be switched from the
V
this time the clock registers will be maintained by the attached battery supply. On power-up,
when V
page
For a further, more detailed review of lifetime calculations, please see application note
AN1012.
WRITE mode sequence
CC
Figure 6 on page 10
pin to the battery when V
22,
CC
S
Table 11 on page
Figure 9 on page
ADDRESS
returns to a nominal value, write protection continues for t
CC
SLAVE
applied, the M41T81 can be accessed as described above with READ or
ADDRESS (An)
and again after it has received the word address and each data
11. Following the START condition and slave address, a logic '0'
WORD
23).
CC
Doc ID 7529 Rev 10
falls below the battery backup switchover voltage (V
DATA n
DATA n+1
rec
DATA n+X
(see
Figure 10 on
Operation
P
AI00591
SO
11/29
). At