M41T81MX6 STMicroelectronics, M41T81MX6 Datasheet - Page 12

• Manufacturer Part Number: M41T81MX6
• Description: IC RTC SERIAL W/ALARM 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T81MX6

• Memory Size: 20B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-2822-5

Clock operation
3
Note:
3.1
3.2
12/29
Clock operation
The 20-byte register map (see
the date and time from the clock, in a binary coded decimal format. Tenths/hundredths of
seconds, seconds, minutes, and hours are contained within the first four registers.
The tenths/hundredths of seconds cannot be written to any value other than “00.”
Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY
ENABLE bit (CEB) and the CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle,
either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial
state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of register 04h contain the
day (day of week). Registers 05h, 06h, and 07h contain the date (day of month), month and
years. The ninth clock register is the control register (this is described in the clock calibration
section). Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause
the oscillator to stop. If the device is expected to spend a significant amount of time on the
shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator
restarts within one second.
The eight clock registers may be read one byte at a time, or in a sequential block. Provision
has been made to assure that a clock update does not occur while any of the eight clock
addresses are being read. If a clock address is being read, an update of the clock registers
will be halted. This will prevent a transition of data during the READ.
Power-down time-stamp
When a power failure occurs, the HT bit will automatically be set to a '1.' This will prevent the
clock from updating the TIMEKEEPER
time of the power-down event. Resetting the HT bit to a '0' will allow the clock to update the
TIMEKEEPER registers with the current time. For more information, see application note
AN1572.
Clock registers
The M41T81 offers 20 internal registers which contain clock, alarm, watchdog, flag, square
wave and control data. These registers are memory locations which contain external (user
accessible) and internal copies of the data (usually referred to as BiPORT
external copies are independent of internal functions except that they are updated
periodically by the simultaneous transfer of the incremented internal copy. The internal
divider (or clock) chain will be reset upon the completion of a WRITE to any clock address.
The system-to-user transfer of clock data will be halted whenever the address being read is
a clock address (00h to 07h). The update will resume either due to a stop condition or when
the pointer increments to any non-clock address (08h-13h).
Clock and alarm registers store data in BCD. Control, watchdog and square wave registers
store data in binary format.
Doc ID 7529 Rev 10
Table 2 on page
®
registers, and will allow the user to read the exact
13) is used to both set the clock and to read
™
cells). The
M41T81