M41T65Q6F STMicroelectronics, M41T65Q6F Datasheet

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Features ■ Serial RTC with alarm functions 2 – 400 kHz I C serial interface – Memory mapped registers for seconds, minutes, hours, day, date, month, year, and century – Tenths/hundredths of seconds register ■ 350 nA timekeeping current at ...

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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M41T62/63/64/65 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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List of tables List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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M41T62/63/64/65 List of figures Figure 1. M41T62 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Description 1 Description The M41T6x serial access TIMEKEEPER 32.768 kHz oscillator. Eight registers are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 8 registers provide status/control of alarm, 32 KHz output, calibration, ...

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M41T62/63/64/65 Figure 2. M41T63 logic diagram 1. Open drain. 2. Defaults to 32 KHz on power-up. Figure 3. M41T64 logic diagram 1. Open drain. 2. Defaults to 32 KHz on power-up. Figure 4. M41T65 logic diagram 1. Open drain. V ...

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Description Figure 5. M41T62 connections (1) 4 SQW 1. SQW output defaults to 32 KHz upon power-up. 2. Open drain. Figure 6. M41T63 connections 1. SQW output defaults to 32 KHz upon power-up. ...

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M41T62/63/64/65 Figure 8. M41T65 connections 1. Open drain. Table 2. Signal names XI XO SDA SCL IRQ/OUT IRQ/FT/OUT SQW F 32K WDO Figure 9. M41T62 block diagram (3) XTAL (3) SDA SCL 1. Open drain. 2. ...

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Description Figure 10. M41T63 block diagram XTAL SDA SCL 1. Open drain. 2. Defaults to 32 KHz on power-up. Figure 11. M41T64 block diagram XTAL SDA SCL 1. Defaults enabled on power-up. 2. Open drain. Figure 12. M41T65 block diagram ...

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M41T62/63/64/65 Figure 13. Hardware hookup for SuperCap™ backup operation Diode required on open drain pin (M41T65 only) for SuperCap (or battery) backup. Low threshold BAT42 diode recommended. 2. For M41T62 and M41T65 (open drain). 3. For M41T63 ...

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Operation 2 Operation The M41T6x clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 16 bytes contained in the device can then be ...

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M41T62/63/64/65 2.1.4 Data valid The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may ...

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Operation Figure 15. Acknowledgement sequence SCL FROM MASTER DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER 2.2 READ mode In this mode the master reads the M41T6x slave after setting the slave address (see Figure 17 on page acknowledge bit, ...

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M41T62/63/64/65 Figure 17. READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS Figure 18. Alternative READ mode sequence BUS ACTIVITY: MASTER SDA LINE S BUS ACTIVITY: SLAVE ADDRESS WORD S ADDRESS (An) SLAVE ADDRESS DATA n+X ...

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Operation 2.3 WRITE mode In this mode the master transmitter transmits to the M41T6x slave receiver. Bus protocol is shown in Figure 19 on page (R/W=0) is placed on the bus and indicates to the addressed device that word address ...

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M41T62/63/64/65 3 Clock operation The M41T6x is driven by a quartz-controlled oscillator with a nominal frequency of 32.768 kHz. The accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for ...

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Clock operation 3.1 RTC registers The M41T6x user interface is comprised of 16 memory mapped registers which include clock, calibration, alarm, watchdog, flags, and square wave control. The eight clock counters are accessed indirectly via a set of buffer/transfer registers ...

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M41T62/63/64/65 Write timing When writing to the device, the data is shifted into the M41T62's I edge of the SCL signal. As shown in transferred from the I pointer (not shown). Writes to the clock registers (addresses 0-7) Data written ...

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Clock operation Table 3. M41T62 register map Addr D7 00h 01h ST 02h OFIE 03h 0 04h RS3 05h 0 06h CB1 07h 08h OUT 09h RB2 BMB4 BMB3 0Ah AFE SQWE 0Bh RPT4 RPT5 0Ch RPT3 0Dh RPT2 0Eh ...

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M41T62/63/64/65 Table 4. M41T63 register map Addr D7 D6 00h 0.1 seconds 01h ST 02h 0 03h 0 04h RS3 RS2 05h 0 06h CB1 CB0 07h 08h 0 09h RB2 BMB4 BMB3 0Ah 0 SQWE 0Bh RPT4 RPT5 0Ch ...

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Clock operation Table 5. M41T64 register map Addr D7 00h 0.1 seconds 01h ST 02h 0 03h 0 04h RS3 RS2 05h 0 06h CB1 CB0 07h 08h 0 09h RB2 BMB4 0Ah 0 SQWE 0Bh RPT4 RPT5 0Ch RPT3 ...

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M41T62/63/64/65 Table 6. M41T65 register map Addr D7 00h 01h ST 02h OFIE 03h 0 04h 0 05h 0 06h CB1 CB0 07h 08h OUT 09h RB2 BMB4 0Ah AFE 0Bh RPT4 RPT5 0Ch RPT3 0Dh RPT2 0Eh RPT1 0Fh ...

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Clock operation 3.2 Calibrating the clock The M41T6x real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. This provides the time-base for the RTC. The accuracy of the clock depends on the frequency ...

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M41T62/63/64/65 Figure 21. Crystal accuracy across temperature Frequency (ppm –20 –40 –60 –80 –100 –120 –140 –160 –40 –30 Figure 22. Calibration waveform NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION Δ – –0.036 ...

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Clock operation 3.3 Setting alarm clock registers Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, ...

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M41T62/63/64/65 3.4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier ...

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Clock operation 3.6 Square wave output (M41T62/63/64) The M41T62/63/64 offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 04h establish the square wave output frequency. These frequencies are listed in ...

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M41T62/63/64/65 3.8 Century bits These two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. See 3.9 Output driver pin (M41T62/65) When the OFIE bit, AFE bit, and watchdog register ...

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Clock operation 3.11 Initial power-on defaults Upon application of power to the device, the register bits will initially power-on in the state indicated in Table Table 9. Initial power-on default values Condition Device ST OF OFIE OUT FT AFE SQWE ...

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M41T62/63/64/65 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions ...

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DC and AC parameters 5 DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived ...

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M41T62/63/64/65 Table 13. Capacitance Symbol C IN (3) C OUT Effective capacitance measured with power supply at 3.6 V; sampled only, not 100% tested 25° MHz. 3. Outputs deselected. Table 14. DC ...

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DC and AC parameters Table 15. Crystal electrical characteristics Sym f Resonant frequency O R Series resistance (T = – °C, oscillator startup at 2 Load capacitance L 1. For the QFN16 package, user-supplied ...

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M41T62/63/64/65 Table 17. Oscillator characteristics Symbol Oscillator start voltage V STA t Oscillator start time STA C XIN capacitance g C XOUT capacitance d IC-to-IC frequency variation 1. Reference value. T • ...

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Package mechanical information 6 Package mechanical information In order to meet environmental requirements, ST offers these devices in different grades of ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available ...

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M41T62/63/64/65 Figure 27. QFN16 – 16-pin, quad, flat package, no-lead body size, outline Note: Drawing is not to scale. Table 19. QFN16 – 16-pin, quad, flat package, no-lead body size, ...

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Package mechanical information Figure 28. QFN16 – 16-pin, quad, flat package, no-lead mm, recommended footprint Note: Dimensions shown are in millimeters (mm). Figure 29. LCC8 — 8-pin 1 3.2 mm leadless chip carrier Note: Dimensions ...

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M41T62/63/64/65 Figure 30. Carrier tape for QFN16 3mm package T TOP COVER TAPE K 0 Table 20. Carrier tape dimensions for QFN16 package Package 1.50 12.00 1.75 +0.10 QFN16 ...

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Package mechanical information Figure 32. Reel schematic D A Full radius Table 21. Reel dimensions for 12 mm carrier tape - QFN16 and LCC8 packages A B (max) (min) 330 mm 1.5 mm (13-inch) Note: The dimensions given in parameters. ...

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M41T62/63/64/65 7 Part numbering Table 22. Ordering information scheme Example: Device family M41T Device type and supply voltage ...

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Revision history 8 Revision history Table 23. Document revision history Date 26-Jan-2010 07-May-2010 25-May-2010 24-Mar-2011 42/43 Revision Minor textual changes; updated 12 Table 11; footnote 1 in Updated title of datasheet, Features, 3.4, 3.10, Section 4, Figure 13 embedded crystal ...

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... M41T62/63/64/65 Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...