MPC9608AC Freescale Semiconductor, MPC9608AC Datasheet
MPC9608AC
Specifications of MPC9608AC
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MPC9608AC Summary of contents
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... LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the incident edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an effective fanout of 1:20. The device is packaged in a 7x7 mm © Freescale Semiconductor, Inc., 2004. All rights reserved. Rev 4, 10/2004 MPC9608 LOW VOLTAGE 3 ...
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... Figure 2. MPC9608 32-Lead Package Pinout (Top View) MPC9608 2 CCLK PLL STOP VCO Figure 1. MPC9608 Logic Diagram MPC9608 Bank A QA0 QA1 QA2 QA3 QA4 Bank B QB0 QB1 ÷ 2 QB2 QB3 QB4 PLL feedback QFB QB4 14 QB3 13 QB2 12 GND 11 QB1 10 QB0 Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Advanced Clock Drivers Device Data Freescale Semiconductor PLL reference clock signal PLL feedback signal input, connect to a QFB output PLL frequency range select Frequency divider select for bank B outputs PLL enable/disable Output enable/disable (high-impedance tristate) Synchronous clock enable/stop Clock outputs PLL feedback signal output. Connect to FB_IN Negative power supply PLL positive power supply (analog power supply) ...
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... Alternatively, the device drives up to two 50 Ω series terminated transmission lines. TT Max Unit Condition ÷ Per output pF Inputs Max Unit Condition ±20 mA ±50 mA °C 125 Max Unit Condition V + 0.3 V LVCMOS CC 0.8 V LVCMOS - 0. 0. Ω ±200 µ GND Pin CCA 4.0 mA All V Pins CC Advanced Clock Drivers Device Data Freescale Semiconductor (1) ...
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... Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two. 5. Calculation of reference duty cycle limits 100 MHz the input duty cycle range is 20% < DC < 80%. REF point of PLL transfer characteristics. Advanced Clock Drivers Device Data Freescale Semiconductor (1) = -40° to 85°C) A Min (2) F_RANGE = 00 ...
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... MPC9608 V CCLK CC Common QFB Device 1 Any Q are Device 1 F QFB Device2 Any Q Device 2 Max. skew Figure 4. MPC9608 Maximum Device-to-Device Skew . + ∅ SK(O) PD, LINE(FB) JIT PD,LINE(FB) -t (∅) t JIT(∅) +t SK(O) +t (∅) t JIT(∅) +t SK(O) t SK(PP) Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is re- ferred to Freescale Semiconductor application note AN1091. In most high performance clock networks point-to-point distri- bution of signals is the method of choice point-to-point scheme either series terminated or parallel terminated trans- mission lines can be used ...
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... Figure 8. CCLK MPC9608 AC Test Reference for V MPC9608 8 MPC9608 Output Buffer 14 Ω Figure 7. Optimized Dual Line Termination should MPC9608 DUT = 50 Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω Ω 25 Ω Ω Ω Ω 3 Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Figure 11. Output Duty Cycle (DC) T JIT(CC The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. Figure 13. Cycle-to-Cycle Jitter Figure 15. Output Transition Time Test Reference Advanced Clock Drivers Device Data Freescale Semiconductor V CC ÷ CCLK CC GND V CC ÷ FB_IN CC GND Figure 10 ...
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... A2 1.35 1.45 b 0.30 0.45 b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.50 0.70 L1 1.00 REF q 0˚ 7˚ REF R1 0.08 0.20 R2 0.08 --- S 0.20 REF Advanced Clock Drivers Device Data Freescale Semiconductor ...
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... Advanced Clock Drivers Device Data Freescale Semiconductor NOTES MPC9608 11 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...