FS6370-01G-XTD ON Semiconductor, FS6370-01G-XTD Datasheet - Page 4

• Manufacturer Part Number: FS6370-01G-XTD
• Description: IC CLOCK GEN 3-PLL EEPROM 16SOIC
• Manufacturer: ON Semiconductor
• Type: PLL Clock Generatorr

Specifications of FS6370-01G-XTD

• Pll: Yes
• Input: Crystal
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:4
• Differential - Input:output: No/No
• Frequency - Max: 230MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Frequency-max: 230MHz
• Mounting Style: SMD/SMT
• Max Input Freq: 230 MHz
• Max Output Freq: 27 MHz
• Number Of Outputs: 1
• Operating Supply Voltage: 5 V to 3.3 V
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 43 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 766-1025

FS6370
achieve a desired input-frequency-to-output-frequency ratio without making both the reference and feedback divider values
comparatively large. Generally, very large values are undesirable as they degrade the bandwidth of the PLL, increasing phase jitter and
acquisition time.
To understand the operation of the feedback divider, refer to Figure 4. The M-counter (with a modulus always equal to M) is cascaded
with the dual-modulus pre-scaler. The A-counter controls the modulus of the pres-caler. If the value programmed into the A-counter is
A, the pre-scaler will be set to divide by N+1 for A pre-scaler outputs. Thereafter, the prescaler divides by N until the M-counter output
resets the A-counter, and the cycle begins again. Note that N=8, and A and M are binary numbers.
Suppose that the A-counter is programmed to zero. The modulus of the pre-scaler will always be fixed at N; and the entire modulus of
the feedback divider becomes MxN.
Next, suppose that the A-counter is programmed to a one. This causes the pre-scaler to switch to a divide-by-N+1 for its first divide
cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the
feedback divider. The overall modulus is now seen to be equal to MxN+1.
This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A<M.
3.1.3. Feedback Divider Programming
For proper operation of the feedback divider, the A-counter must be programmed only for values that are less than or equal to the M-
counter. Therefore, not all divider moduli below 56 are available for use. This is shown in Table 2.
Above a modulus of 56, the feedback divider can be programmed to any value up to 2047.
Table 2: Feedback Divider Modulus Under 56
3.2 Post Divider Muxes
As shown in Figure 2, a mux in front of each post divider stage can select from any one of the three PLL frequencies or the reference
frequency. The mux selection is controlled by bits in the EEPROM or the control registers.
The input frequency on two of the four multiplexers (muxes C and D in Figure 2) can be altered without reprogramming by a logic-level
input on the SEL_CD pin.
M-Counter:
FBKDIV[10:3]
00000001
00000010
00000011
00000100
00000101
00000110
00000111
000
16
24
32
40
48
56
8
001
17
25
33
41
49
57
9
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010
18
26
34
42
50
58
-
Figure 4: Feedback Divider
Feedback Divider Modulus
A-Counter: FBKDIV[2:0]
011
27
35
43
51
59
-
-
100
36
44
52
60
-
-
-
101
45
53
61
-
-
-
-
110
54
62
-
-
-
-
-
111
63
-
-
-
-
-
-