IDT5V9950PFI IDT, Integrated Device Technology Inc, IDT5V9950PFI Datasheet - Page 8

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IDT5V9950PFI

Manufacturer Part Number
IDT5V9950PFI
Description
IC CLK DVR PLL 1:8 200MHZ 32TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
TurboClock™ II JRr
Type
Driver, PLLr
Datasheet

Specifications of IDT5V9950PFI

Pll
Yes with Bypass
Input
LVTTL
Output
LVTTL
Number Of Circuits
1
Ratio - Input:output
1:8
Differential - Input:output
No/No
Frequency - Max
200MHz
Divider/multiplier
Yes/Yes
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-TQFP, 32-VQFP
Frequency-max
200MHz
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
5V9950PFI
800-1993
IDT5V9950PFI

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT5V9950PFI
Manufacturer:
IDT
Quantity:
125
Part Number:
IDT5V9950PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
AC TIMING DIAGRAM
NOTES:
PE:
Skew:
t
t
t
t
t
t
t
t
REF D IVIDE D B Y 2
REF D IVIDE D B Y 4
SKEWPR
SKEW0
DEV
ODCV
PWH
PWL
ORISE
LOCK
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
:
is measured at 0.8V.
:
:
is measured at 2V.
:
and t
:
INV ER TE D Q
OFALL
The AC Timing Diagram applies to PE=V
of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
The time between the earliest and the latest output transition among all outputs for which the same t
with 75Ω to V
The skew between a pair of outputs (xQ
The skew between outputs when they are selected for 0t
The output-to-output skew between any two devices operating under the same conditions (V
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
The time that is required before synchronization is achieved. This specification is valid only after V
is measured from the application of a new signal or frequency at REF or FB until t
OTH ER Q
are measured between 0.8V and 2V.
RE F
DDQ
FB
Q
/2.
t
(
φ )
t
DD
0
SK EW 1, 3, 4
and xQ
t
t
. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge
t
S KE W P R
SK EW 0, 1
SK EW 3, 4
t
R EF
1
) when all eight outputs are selected for 0t
t
RP W H
U
.
t
O DC V
t
SK EW 3, 4
8
t
S KE W 2
t
R PW L
PD
t
O DC V
is within specified limits.
t
t
S KE W P R
SK EW 0, 1
U
DDQ
.
U
, V
delay has been selected when all are loaded with 20pF and terminated
SKEW2
DD
DD
/V
, ambient temperature, air flow, etc.)
DDQ
and t
is stable and within normal operating limits. This parameter
SKEW4
INDUSTRIAL TEMPERATURE RANGE
specifications.
t
S KE W 2
t
t
SK EW 3, 4
SK EW 2, 4
t
CC JH,M ,L

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