IDT5V9950PFI IDT, Integrated Device Technology Inc, IDT5V9950PFI Datasheet - Page 2

• Manufacturer Part Number: IDT5V9950PFI
• Description: IC CLK DVR PLL 1:8 200MHZ 32TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TurboClock™ II JRr
• Type: Driver, PLLr

Specifications of IDT5V9950PFI

• Pll: Yes with Bypass
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5V9950PFI; 800-1993; IDT5V9950PFI

PIN CONFIGURATION
PIN DESCRIPTION
NOTE:
1. When TEST = MID and sOE = HIGH, PLL remains active with nF[
IDT5V9950
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II JR.
effect unless nF[
Pin Name
TEST
sOE
nQ
nF
GND
V
REF
V
V
GND
FB
PE
FS
DDQ
4Q
4Q
DD
3F
4F
4F
[1:0]
[1:0]
DDQ
PE
(1)
(1)
1
0
1
0
1
1
2
3
4
5
6
7
8
1:0
] = LL.
32
PWR
PWR
PWR
9
Type
OUT
I N
I N
I N
IN
I N
I N
I N
31
10
30
11
TOP VIEW
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary
Table) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q
be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[
disable controls for individual banks when nF[
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
3-level inputs for selecting 1 of 9 skew taps or frequency functions
Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.)
Four banks of two outputs with programmable skew
Power supply for output buffers
Power supply for phase locked loop, lock output, and other internal circuitry
Ground
29
TQFP
12
28
13
27
14
26
15
25
16
24
23
22
20
19
18
17
21
1:0
] = LL functioning as an output disable control for individual output banks. Skew selections remain in
1F
1F
sOE
V
1Q
1Q
GND
GND
DD Q
1
0
0
1
1:0
2
] = LL. Set sOE LOW for normal operation (has internal pull-down).
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
CAPACITANCE
NOTE:
1. Capacitance applies to all inputs except TEST, FS, nF
Parameter
Symbol
V
V
T
STG
DDQ
I
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
C
IN
, V
DD
Supply Voltage to Ground
DC Input Voltage
REF Input Voltage
Maximum Power
Dissipation
Storage Temperature Range
Description
Input Capacitance
0
Description
and 2Q
(T
1
A
) in a LOW state (for PE = H) - 2Q
INDUSTRIAL TEMPERATURE RANGE
= +25°C, f = 1MHz, V
T
T
A
A
= 85°C
= 55°C
[1:0]
Typ.
–0.5 to V
5
–0.5 to +4.6
–0.5 to +5.5
, and DS
–65 to +150
IN
1:0
= 0V)
] pins act as output
Max
0.7
1.1
Max.
DD
0
and 2Q
7
[1:0]
(1)
+0.5
.
1
Unit
Unit
° C
pF
may
W
V
V
V