PIC24FV32KA304-I/PT Microchip Technology, PIC24FV32KA304-I/PT Datasheet - Page 255

• Manufacturer Part Number: PIC24FV32KA304-I/PT
• Description: MCU 32KB FLASH 2KB RAM 44-TQFP
• Manufacturer: Microchip Technology

Specifications of PIC24FV32KA304-I/PT

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TQFP-44
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.0
The PIC24F instruction set adds many enhancements
to the previous PIC
maintaining an easy migration from previous PIC MCU
instruction sets. Most instructions are a single program
memory word. Only three instructions require two
program memory locations.
Each single-word instruction is a 24-bit word divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction. The instruction set is
highly orthogonal and is grouped into four basic
categories:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
Table 28-1
the instructions. The PIC24F instruction set summary
in
status flags affected by each instruction.
Most word or byte-oriented W register instructions
(including
operands:
• The first source operand, which is typically a
• The second source operand, which is typically a
• The destination of the result, which is typically a
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value, ‘f’
• The destination, which could either be the file
Most
rotate/shift instructions) have two operands:
• The W register (with or without an address
• The bit in the W register or file register (specified
 2011 Microchip Technology Inc.
Note:
register ‘Wb’ without any address modifier
register ‘Ws’ with or without an address modifier
register ‘Wd’ with or without an address modifier
register, ‘f’, or the W0 register, which is denoted
as ‘WREG’
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
by a literal value or indirectly by the contents of
register ‘Wb’)
Table 28-2
bit-oriented
INSTRUCTION SET SUMMARY
lists the general symbols used in describing
This chapter is a brief summary of the
PIC24F instruction set architecture and is
not intended to be a comprehensive
reference source.
barrel
lists all the instructions, along with the
shift
instructions
®
MCU instruction sets, while
instructions)
(including
have
simple
three
PIC24FV32KA304 FAMILY
The literal instructions that involve data movement may
use some of the following operands:
• A literal value to be loaded into a W register or file
• The W register or file register where the literal
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
• The first source operand, which is a register ‘Wb’
• The second source operand, which is a literal
• The destination of the result (only if not the same
The control instructions may use some of the following
operands:
• A program memory address
• The mode of the table read and table write
All instructions are a single word, except for certain
double-word
double-word instructions so that all of the required
information is available in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is
executed as an instruction (by itself), it will execute as
a NOP.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter (PC) is changed as a result of the
instruction. In these cases, the execution takes two
instruction cycles, with the additional instruction
cycle(s) executed as a NOP. Notable exceptions are the
BRA
CALL/GOTO,
RETURN/RETFIE instructions, which are single-word
instructions but take two or three cycles.
Certain instructions that involve skipping over the
subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or
two-word instruction. Moreover, double-word moves
require two cycles. The double-word instructions
execute in two instruction cycles.
register (specified by the value of ‘k’)
value is to be loaded (specified by ‘Wb’ or ‘f’)
without any address modifier
value
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
instructions
(unconditional/computed
all
instructions,
table
reads
which
branch),
and
DS39995B-page 255
were
writes,
indirect
made
and