HI-8282J-44 Holt Integrated Circuits, HI-8282J-44 Datasheet - Page 6

• Manufacturer Part Number: HI-8282J-44
• Manufacturer: Holt Integrated Circuits

Specifications of HI-8282J-44

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PLCC
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

FUNCTIONAL DESCRIPTION (cont.)
REPEATER OPERATION
Repeater mode of operation allows a data word received by the
HI-8282 to be placed directly into the Transmit FIFO for
transmission.
receiver shift register, the
on the SEL line and
for normal receiver operation, placing the lower byte (16) of the
data word on the data bus. By strobing
EN, the byte is also transferred into the Transmit FIFO.
then taken high and
word byte onto the data bus. By strobing
EN
FIFO. The data word is now ready for transmission, according to
the parity programmed into the Control Word register.
TIMING DIAGRAMS
ARINC DATA
ENABLE BYTE ON BUS
429DO
429DO
, the second data word byte is also transferred to the Transmit
DATA READY FLAG
BYTE SELECT
After a 32-bit word has been shifted into the
DATA BUS
DATA BUS
CWSTR
EN
BIT 31
EN
DATA
SEL
D/R
is strobed. This is the same procedure as
ARINC BIT
EN
is strobed again to place the upper data
BIT 30
D/R
flag goes low. A logic "0" is placed
NULL
BIT 32
t
PL1
DATA
D/R
DON'T CARE
PL2
at the same time as
at the same time as
BIT 31
DATA RATE - EXAMPLE PATTERN
NULL
HOLT INTEGRATED CIRCUITS
t
ENDATA
t
D/REN
LOADING CONTROL WORD
t
CWSTR
t
RECEIVER OPERATON
SELEN
SEL is
DATA
t
CWSET
HI-8282
BIT 32
,
VALID
6
BYTE 1 VALID
NULL
In normal (non-repeater) operation, either byte of the received
data word may be read first by using the SEL input. During
repeater operation however, data word lower byte must always be
read first. While the data is being read, it is loading concurrently
into the Transmit FIFO, which always loads lower byte first.
MASTER RESET (
Upon Master Reset, data transmission and reception are
immediately terminated, all three FIFOs are cleared as are the
FIFO flags at the device pins and in the Status Register. The
Control Word register is not affected by a Master Reset.
t
ENSEL
t
CWHLD
t
DATAEN
DON'T CARE
WORD GAP
t
ENEN
MR
t
ENDATA
)
t
SELEN
t
END/R
t
EN
NEXT WORD
BYTE 2 VALID
BIT 1
t
ENSEL
DON'T CARE
t
DATAEN