HI-8282J-44 Holt Integrated Circuits, HI-8282J-44 Datasheet
HI-8282J-44
Specifications of HI-8282J-44
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HI-8282J-44 Summary of contents
Page 1
... ARINC 429 specifications for loading, level detection, timing, and protocol. section provides the ARINC 429 communication protocol. An external line driver such as the Holt HI-8585 or HI-3182 is required to translate the 5 volt logic outputs to ARINC 429 drive levels. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers ...
Page 2
... Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. "ONES" data output from transmitter. ...
Page 3
... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-8282 contains 10 data flip flops whose D inputs are con- nected to the data bus and clocks connected to flip flop provides options to the user as follows: DATA BUS FUNCTION CONTROL PIN If enabled, an internal connection BDO5 SELF TEST 0 = ENABLE ...
Page 4
... When the receive sig- nal is outside the differential voltage range defined for any shift register, a low bit is clocked. Only one shift register can clock a high bit for any given sample. All three registers clock low bits if the differential input voltage is between de- fined state voltage bands ...
Page 5
... The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. SELF TEST If the BD05 control word bit is set low, the digital outputs of the ...
Page 6
... In normal (non-repeater) operation, either byte of the received data word may be read first by using the SEL input. During repeater operation however, data word lower byte must always be read first. While the data is being read loading concurrently into the Transmit FIFO, which always loads lower byte first. MASTER RESET ( ...
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... TX/R ENTX t ENDAT 429DO or 429DO BIT 32 429DI D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TX/R ENTX 429DO HI-8282 TRANSMITTER OPERATION BYTE 1 VALID t DWSET t DWHLD PL12 TRANSMITTING DATA ARINC BIT DATA DATA BIT 1 BIT 2 REPEATER OPERATION TIMING t END ENEN EN ...
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... To Vcc R H Input Sink I IH Input Source I IL Differential C Pins GND Vcc C H Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source Output Sink Output Source OUT Output Sink Output Source I ...
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... Setup - DATA BUS Valid to Hold - Delay - TRANSMISSION TIMING Spacing - Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH ...
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... ADDITIONAL HI-8282 PIN CONFIGURATIONS (See page 1 for the 40-pin Ceramic Side-Brazed DIP Package ) 44-PIN PLASTIC PLCC HI-8282J-44 HI-8282JT-44 44-PIN CERAMIC LCC HI-8282 44-PIN J-LEAD CERQUAD HI-8282S HI-8282ST HI-8282SM-01 HOLT INTEGRATED CIRCUITS 10 HI-8282U HI-8282UT ...
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... PART NUMBER Blank F PART NUMBER Blank T PART NUMBER 8282J Notes: (4) NOT RECOMMENDED FOR NEW DESIGNS. The newer HI-8282APJI and HI-8282APJT replace the HI-8282J-44 and HI-8282JT-44 respectively. HI-8282 TEMPERATURE BURN FLOW RANGE IN I -40°C to +85°C No -55°C to +125° -55°C to +125°C ...
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... REVISION HISTORY Revision Date Description of Change DS8282, Rev. G 02/23/09 Clarified the “T” temperature range. Clarified Note (4) in Ordering Information. HI-8282 HOLT INTEGRATED CIRCUITS 12 ...
Page 13
... Standard 95) 44-PIN J-LEAD CERQUAD .650 ±.010 (16.510 ±.254) SQ. .039 ±.005 (.990 ±.127) .019 ±.002 (.483 ± .051) HI-8282 PACKAGE DIMENSIONS 2.020 max (51.308) .595 ±.010 (15.113 ±.254) .050 typ (1.270) .085 ±.009 (2.159 ± ...
Page 14
... SQ. .173 ±.008 (4.394 ±.203) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN CERAMIC LEADLESS CHIP CARRIER .020 INDEX PIN 1 (.508) .651 ±.011 (16.535 ±.279) SQ. ...