SCAN926260TUF National Semiconductor, SCAN926260TUF Datasheet - Page 13

• Manufacturer Part Number: SCAN926260TUF
• Manufacturer: National Semiconductor

Specifications of SCAN926260TUF

• Number Of Elements: 6
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 50mV
• Diff. Input Low Threshold Volt: -50mV
• Output Type: Deserializer
• Transmission Data Rate: 660Mbps
• Power Dissipation: 3.7W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: LBGA
• Number Of Receivers: 1
• Number Of Drivers: 10
• Lead Free Status / RoHS Status: Not Compliant

ternal Failsafe Biasing. Please see Figure 11 for the Failsafe
Biasing Setup.
DIFFERENCES BETWEEN the DS92LV1260, the
SCAN921260, and the SCAN926260
The DS92LV1260 is a six channel, ten bit, Bus LVDS Dese-
rializer with random lock capability and a parallel clock rate
up to 40MHz. Each channel contains a recovered clock
(RCLKn) and lock (LOCKn) output. The DS92LV1260 also
contains a seventh serial input channel that serves as a re-
dundant input. Also, unlike previous deserializers, the
LOCKn signal is synchronous to valid data appearing on the
outputs. Please see the DS92LV1260 datasheet for more
specific details about the seventh redundant channel and fur-
ther details.
The SCAN921260 contains the same basic functions as the
DS92LV1260. However, the SCAN921260 has an increased
parallel clock rate up to 66MHz, is IEEE 1149.1 (JTAG) com-
pliant and also contains at-speed Built-In-Self-Test (BIST).
The SCAN926260 contains the same basic functions as the
SCAN921260. However, in addition to a master powerdown,
the SCAN926260 has individual powerdown pins per chan-
nel, has eliminated the seventh redundant channel, and now
asserts all outputs ROUTn[0:9] and RCLKn high during pow-
erdown and during loss of lock. Please also note that the
LOCKn pin output is no longer affected by REN. Also, the
SCAN926260 is footprint compatible and may be used inter-
changibly with the SCAN921260.
USING NOISE MARGIN TO VALIDATE SIGNAL QUALITY
The parameters t
first measuring how much of the ideal bit the receiver needs
to ensure correct sampling. After determining this amount,
what remains of the ideal bit that is available for external
sources of noise is called noise margin. Noise margin does
not include transmitter jitter. Please see Figure 8 for a graph-
ical explanation. Also, for a more detailed explanation of noise
margin, please see Application Note 1217 titled "How to Val-
idate BLVDS SER/DES Signal Integrity Using an Eye Mask."
The vertical limits of the mask are determined by the
SCAN926260 receiver input threshold of ±50mV.
BYPASS
Circuit board layout and stack-up for the BLVDS devices
should be designed to provide noise-free power to the device.
Good layout practice will also separate high-frequency or
high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (4
to 10 mils) for power / ground sandwiches. This increases the
intrinsic capacitance of the PCB power system which im-
proves power supply filtering, especially at high frequencies,
and makes the value and placement of external bypass ca-
pacitors less critical. External bypass capacitors should in-
clude both RF ceramic and tantalum electrolytic types. RF
capacitors may use values in the range of 0.01 uF to 0.1 uF.
Tantalum capacitors may be in the 2.2 uF to 10 uF range.
Voltage rating of the tantalum capacitors should be at least
3X the power supply voltage being used.
It is a recommended practice to use two vias at each power
pin as well as at all RF bypass capacitor terminals. Dual vias
reduce the interconnect inductance by up to half, thereby re-
ducing interconnect inductance and extending the effective
frequency range of the bypass components. Locate RF ca-
pacitors as close as possible to the supply pins, and use wide
low impedance traces (not 50 Ohm traces). Surface mount
capacitors are recommended due to their smaller parasitics.
RNMI-LEFT
and t
RNMI-RIGHT
are calculated by
13
When using multiple capacitors per supply pin, locate the
smaller value closer to the pin. A large bulk capacitor is rec-
ommend at the point of power entry. This is typically in the
50uF to 100uF range and will smooth low frequency switching
noise.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter may be used to provide clean power to
sensitive circuits such as PLL circuitry.
Use at least a four layer board with a power and ground plane.
Locate CMOS (TTL) signals away from the LVDS lines to
prevent coupling. Closely-coupled differential lines of 100
Ohms Z
nects. The closely-coupled lines help to ensure that coupled
noise will appear as common-mode and is rejected by the re-
ceivers. Also, the tight coupled lines will radiate less.
Termination of the LVDS interconnect is required. For point-
to-point applications, termination should be located at the
load end. Nominal value is 100 Ohms to match the line's dif-
ferential impedance. Place the resistor as close to the receiv-
er inputs as possible to minimize the resulting stub between
the termination resistor and receiver.
Additional general guidance can be found in the LVDS
Owner's Manual - available in PDF format from the national
web site at: www.national.com/lvds. For packaging informa-
tion on BGA's, please see AN-1126.
Guidance for the SCAN926260 is provided next:
SCAN926260: SIX 1 TO 10 DESERIALIZERS
General guidance is provided below. Exact guidance can not
be given as it is dictated by other board level /system level
criteria. This includes the density of the board, power rails,
power supply, and other integrated circuit power supply
needs.
DVDD = DIGITAL SECTION POWER SUPPLY
These pins supply the digital portion and receiver output
buffers of the device. Receiver DVDD pins require more by-
pass to power outputs under synchronous switching condi-
tions. An estimate of local capacitance requires a minimum of
20nF. This is calculated by taking 66 (60 LVTTL Outputs + 6
RCLK Outputs) times the maximum output short circuit cur-
rent (IOS) of 85mA. Multiplying this number by the maximum
rise time (t
droop in VDD (assume 50mV) yields 448.8nF. Dividing this
number by the number of DVDD pins (25) yields 18nF.
Rounding up to a standard value, 0.1uF is selected for each
DVDD pin. The capacitative bandwidth for this capacitor may
be extended by placing a 0.01uF capacitor in parallel. The
0.01uF capacitor should be placed closer to the DVDD pin
than the 0.1uF capacitor.
PVDD = PLL SECTION POWER SUPPLY
The PVDD pin supplies the PLL circuit. PLL circuits require
clean power for the minimization of jitter. A supply noise fre-
quency in the 300kHZ to 1MHz range can cause increased
output jitter. Certain power supplies may have switching fre-
quencies or high harmonic content in this range. If this is the
case, filtering of this noise spectrum may be required. A notch
filter response is best to provide a stable VDD, suppression
of the noise band, and good high-frequency response (clock
fundamental). This may be accomplished with a pie filter
DIFF
CLH
are typically recommended for LVDS intercon-
) of 4ns and dividing by the maximum allowed
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