SCAN926260TUF National Semiconductor, SCAN926260TUF Datasheet - Page 10

• Manufacturer Part Number: SCAN926260TUF
• Manufacturer: National Semiconductor

Specifications of SCAN926260TUF

• Number Of Elements: 6
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Differential Input High Threshold Voltage: 50mV
• Diff. Input Low Threshold Volt: -50mV
• Output Type: Deserializer
• Transmission Data Rate: 660Mbps
• Power Dissipation: 3.7W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: LBGA
• Number Of Receivers: 1
• Number Of Drivers: 10
• Lead Free Status / RoHS Status: Not Compliant

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REN = Low,
REN = Low,
Powerdown
Powerdown
SCAN926260 Control Signal Truth Table
Not Locked
Not Locked
Key:
Z = High Impedance
X = Don’t Care
10 @ Z = All 10 ROUT for the respective Channel are High Impedance
1 = High Voltage Level
0 = Low Voltage Level
SCAN_HIZB = the internal control signal from the HighZ command at the TAP Controller
SCAN_BIST = the internal control signal from the BIST command at the TAP Controller
Notes:
1) JTAG/SCAN has the highest priority. SCAN_HIZB is active low and SCAN_BIST is active high. If either control is active, the outputs will be in TRI-STATE.
2) MS_PWRDWN has the second highest priority. When MS_PWRDWN is low, the entire chip enters sleep mode and all outputs (ROUTn[0:9], RCLK[n], and
LOCK[n]) are high.
3) PWRDWN[n] are the six individual power-down pins. Each will power down the respective channel. A special case occurs when all six PWRDWN[n] pins are
low-the common bias circuits will also be powered down. This state is equivalent to the case when MS_PWRDWN is low.
4) REN has a lower priority than PWRDWN[n]. When REN is low, the output data (ROUTn[0:9] and RCLK[n]) will be in TRI-STATE. The LOCK[n] signal’s output
is not affected by REN.
5) During normal operation mode (no SCAN, no Power-down, and REN high), LOCK[n] controls the ROUTn[0:9] and RCLK[n] outputs. When LOCK[n] is high
(unlocked), all outputs will be 1, and when LOCK[n] is low (locked), both data and clock will be valid at the outputs. BIST-ALONE mode is considered part of
normal operation and can be overriden by any of the above priorities.
6) There are internal pull-downs on the REN, PWRDWNn and MS_PWRDWN pins. Active operation requires asserting these pins high.
(Note 4, 6)
(Note 4, 6)
(Note 1)
(Note 1)
(Note 2)
(Note 3)
Normal,
(Note 5)
Normal,
(Note 5)
STATE
Locked
Locked
SCAN
SCAN
Default State (Note 6)
SCAN Mode Internal Signals
SCAN_HIZB
0
1
1
1
1
1
1
1
SCAN_BIST
X
1
0
0
0
0
0
0
MS_PWRDWN
X
X
0
1
1
1
1
1
0
10
INPUTS
PWRDWN[n]
All 6 @ 0
X
X
X
1
1
1
1
0
REN
X
X
X
X
1
1
0
0
0
LOCK[n]
Z
Z
1
1
1
0
1
0
1
ROUTn[0:9]
OUTPUTS
10 @ Z
10 @ Z
10 @ Z
10 @ Z
10 @ 1
10 @ 1
10 @ 1
10 @ 1
data
RCLK[n]
clock
Z
Z
Z
Z
1
1
1
1