MC44724AVFU Freescale, MC44724AVFU Datasheet - Page 5

• Manufacturer Part Number: MC44724AVFU
• Manufacturer: Freescale

Specifications of MC44724AVFU

• Lead Free Status / RoHS Status: Not Compliant

Fig 1 : DVIA/DVIB Data Input Timing
Fig 2 : Sync Data Output Timing
[Function Descriptions]
Input Clock 27MHz
Reset Procedure
RESET is a level sensitive input pin. Driving the RESET pin low causes a DVE reset. The 27Mhz DVE
clock signal must be active before RESET is released. De-asserting reset will latch the status of the PAL/
NTSC, Vmute and SEL pins.
The PAL/NTSC pin determines the default values for the DVE control registers. The default register
values have been chosen so that standard PAL or NTSC video will appear at the DAC outputs immediately
when a valid input digital video data stream is present and Vmute is Low at reset.
The Vmute pin controls the "out of reset" operation of the Analog output signals. When "1" at reset, the
video output is muted - output signal is "black - sync". When "0" at reset, the video output is from the
input video data. This control can be used to mute the disable noise signals from a MPEG decoder at reset
until a clear and stable picture is available.
The value on the SEL pins determine the default serial communication mode. If Low, the DVE use I2C bus
operation. If High, the DVE use 4-wired SPI operation.
After reset, the VBI signals (Closed-Caption, CGMS and WSS ) are disabled.
(see page --- for sub-address register descriptions.)
Clock
27.0MHz. This signal on the clock pin needs to be active and stable for 5 cycles before the reset pin is
de-asserted.
Input Data
DVIA/DVIB
Output Data
TP
Output data
H/VF sync
Clock 27MHz
This document contains information on a new product. Specifications and information herein are subject to change without notice.
For More Information On This Product,
50%
Tds
Tdh
Go to: www.freescale.com
Td
No.
5
Td
MC44724A/5A Rev 0.05 07/15/98