MC44724AVFU Freescale, MC44724AVFU Datasheet - Page 42

• Manufacturer Part Number: MC44724AVFU
• Manufacturer: Freescale

Specifications of MC44724AVFU

• Lead Free Status / RoHS Status: Not Compliant

<<<<<<<< I2C-BUS Format >>>>>>
I2C-BUS Slave Receiver Sub-address map
70h:[7]
71h:[7]
72h:[7]
73h[7:0]
74h[7:0]
75h[7:0]
76h[7]
77h[7:5]
78h[7:0]
79h[1:0]
79h[7:2]
S | Slave_address(W) | A | Sub_address | A | Data0 | A | ... | DataN | A | P
S
Slave_address
A
Sub_address
Data0
DataN
P
<<<<<<<< SPI-Bus Format >>>>>>
** WRITE MODE **
S | Write Command | Sub_address | Data0 | ... | DataN | P
S
Write Command
Sub_address
Data0
DataN
P
[6]
[5]
[4]
[3]
[2]
[1:0]
[4:2]
[1:0]
** WRITE MODE **
[6]
[5]
[4]
[3]
[2:0]
[6]
[5]
[4]
[3]
[2]
[1:0]
[6]
[5]
[4:2]
[1:0]
This document contains information on a new product. Specifications and information herein are subject to change without notice.
burst control (default 0:on)
self counter reset switch (default 0:off)
color bar select (default 0:Luma 100% Chroma 75%)
vertical blanking switch(default 0:off)
48 pin output mode select (Csync:1, Flame sync:0)
F/Vsync select(default 0:Vsync)
Master/Slave mode select(default 01:656_slave)
interlaced / non-interlaced
(default 0:interlaced)
VBI input control on 48 pin (default 0:off)
horizontal sync polarity (default 0)
vertical sync polarity (default 0)
frame sync polarity (default 0)
hsync delay control (default 100:0 clock delay)
(In slave mode can use with 7A[7:0])
sub-carrier phase synchronization(default 0)
Test mode (default 0:off)
48 pin I/O switch(default 1:cysnc output)
color bar generate(default 0:off)
setup level control(default 1:7.5IRE)
625lines50Hz/525Lines60Hz
(default set PAL/NTSC pin)
PAL/NTSC (default set PAL/NTSC pin)
00:NTSC/M
01:PAL/BDGHI
(10:PAL/M) (11:PAL/N)
VBI LUMA level register(default 80h)
Burst U_register(default 79d:ntsc/157d:PAL)
Burst V_register(default 128d:ntsc/107d:PAL)
Cr on/off (default 0:on)
Cb on/off (default 0:on)
Luma on/off(default 0:on)
(default 0: on)
1pin dac/4pin dac/7pin dac on/off(default 0: on)
1st set D/A converter output signal control
(default 00 : CBVS/Y/C output)
B/R/G signal control (default 0: On)
17pin dac/20pin dac/23pin dac on/off(default 0: on)
2ndt set D/A converter output signal control
(default 01 : R/G/B output)
sub-carrier phase control(default 00h)
sub-carrier phase control(default 00)
n.a.
Start condition
40(hex) or 1E(hex)
Acknowledge generated by DVE
Sub_address register
First data
Continued data(address is auto incremented)
Stop condition
Chip select on (High to Low)
40(hex) or 1E(hex)
Sub_address byte
First data
Continued data byte(address is auto incremented)
Chip select off (Low to High)
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No.
42
6Eh[7:4]
6Eh[3]
6Eh[2]
6Eh[1:0]
6F[7:6]
6F[5:0]
7A[7:0]
7B[7:6]
7C[7]
80~82h
80~81h
83h[7:0]
84h[7:0]
85h[7:0]
86h[7:0]
87h[7:6]
7D[7:0]
7E[7:2]
[5:2]
[2:1]
[1:0]
7Fh
[5]
[4]
[3]
[2]
[1]
[0]
[1]
[0]
[6]
[5]
[4]
[3]
[0]
n.a.
Cb/Cr gain control
Y mode switch
M2/Beta Cam select
n.a.
Interpolation filter switch
hsync-delay control
(In slave mode, is valid with 71h[2:0] register)
n.a..
Cr/Cb clock timing delay in 16-bit digital input mode
(default 00: clock delay 0)
Y clock timing delay in 16-bit digital input mode
(default 0: clock delay 0)
16-bit multiplexed CbYCrY digital video input mode
(default 0: 8-bit YCrCb digital video input mode)
Ysync signal On/Off(YCrCb mode only)(default 0: On)
R/Bsync signal On/Off(default 0: Off)
Gsync signal On/Off(default 0: Off)
R/B CGMS data insertion On/Off(default 0: On)
G CGMS data insertion On/Off(default 0: On)
RGB/CbCr burst On/Off(default 0: On)
Chroma burst On/Off(default 0: On)
delay on Vsync with reference to DVIA/DVIB data in slave
mode
n.a.
delay on Vsync with reference to DVIA/DVIB data in slave
mode
DVE Version number
CGMS characters for field1(line20)/field2(line283)
WSS characters for field1(line23)
CC character1(line21) (default 'h80)
CC character2(line21) (default 'h80)
CC character1(line284) (default 'h80)
CC character2(line284) (default 'h80)
Closed Caption Status Flag for field2
Automatic set to null code(Closed Caption data)
Automatic generate CC parity bit (default 0: off)
WSS information data insertion on/off (default 0: off)
CGMS on/off (default 0: off)
CC closed caption/extended data for field2 encoding
(default 0: off)
CC closed caption/extended data for field1 encoding
(default 0: off)
MC44724A/5A Rev 0.05 07/15/98