mc44724 Freescale Semiconductor, Inc, mc44724 Datasheet
mc44724
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mc44724 Summary of contents
Page 1
... On Chip Color - bar Generator • +3.3V Power Supply or +3.3V(Digital)/+5V(Analog) Power Supply The MC44724 device is protected by U.S. patent number 4,631,603,4,577,216 and 4,819,098 and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per- view uses only, unless otherwise authorized in writing by Macrovision ...
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... DAVdd 14 VReff2 15 Ibias2 16 NC This document contains information on a new product. Specifications and information herein are subject to change without notice. MC44724 MC44725 No. 2 EXT 48 TVIN 47 DVIN0 46 DVIN1 45 DVIN2 44 DVIN3 43 DVIN4 42 DVIN5 41 DVIN6 40 DVIN7 39 DVss 38 DVdd 37 SEL 36 SCL/SCK 35 SDA/ MC44724/5 Rev 0.21 03/25/97 ...
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... Rec656/601) input in 16-bit input mode, or Test data input/output (TP1 : LSB) 62 TP0 I/O Test data inout/output 63 DLVdd Power Supply D/A Converter Digital circuit 64 DLVss Ground for D/A Coverter Digital circuit This document contains information on a new product. Specifications and information herein are subject to change without notice. DESCRIPTIONS No. 3 MC44724/5 Rev 0.21 03/25/97 ...
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... This document contains information on a new product. Specifications and information herein are subject to change without notice. copy Sync_generator protection BG CGMS, CC_gen WSS_gen 0 0 off_set Modulator 0 0 subcarrier gen 0 0 RGB matrix 0 TEST MC44724/5 40/41(hex) 1D/1E(hex) No. 4 Y/G1Vdd CVBS/Cb/B1Vdd bus C/Cr/R1Vdd Y/G1 Y/G1 CVBS/Cb/B1 CVBS/Cb/B1 C/Cr/R1 C/Cr/R1 Vref1 Ibias1 Y/G2 Y/G2 CVBS/Cb/B2 CVBS/Cb/B2 C/Cr/R2 C/Cr/R2 Vref2 Ibias2 bus DAVdd DAVss MC44724/5 Rev 0.21 03/25/97 ...
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... Input Clock 27MHz Input Data DVIN0~7 Fig 2 : Sync Data Output Timing Clock 27MHz Output Data TP0~8 Output data H/VF sync This document contains information on a new product. Specifications and information herein are subject to change without notice. 50% Tds Tdh Td No MC44724/5 Rev 0.21 03/25/97 ...
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... Hsync polarity sub-address71[5] 244T No. 6 70(hex){[1:0]=01} 1440T 718 718 719 2 2 718 718 719 718 718 718 718 MC44724/5 Rev 0.21 03/25/97 00 ...
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... No. 7 70(hex){[1:0]=01} 1440T 718 Y 718 719 2 2 718 718 719 718 718 718 718 sub-address71[ 273 283 284 285 MC44724/5 Rev 0.21 03/25/97 00 ...
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... Fsync polarity sub-address71[3] Vsync polarity sub-address71[ Fsync polarity sub-address71[3] Vsync polarity sub-address71[ No. 8 sub-address71[ 334 335 320 321 sub-address71[ sub-address71[ MC44724/5 Rev 0.21 03/25/97 ...
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... This document contains information on a new product. Specifications and information herein are subject to change without notice. 0.148uS 27.04uS 63.56uS 0.222uS 27.26uS 64.00uS Fsync polarity sub-address71[4] Hsync Delay sub-address 7A[7:0], 71[3: 266 267 9 No. NTSC 0.148uS 4.74uS PAL 0.222uS 4.74uS sub-address71[1:0] =10, 11 Vsync polarity sub-address71[ 268 269 MC44724/5 Rev 0.21 03/25/97 ...
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... Even field Fsync Vsync Hsync CSYNC This document contains information on a new product. Specifications and information herein are subject to change without notice. Fsync polarity sub-address71[4] Hsync Delay sub-address 7A[7:0], 71[3: 313 314 No. 10 sub-address71[1:0] =10, 11 Vsync polarity sub-address71[ 315 316 MC44724/5 Rev 0.21 03/25/97 ...
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... DACs can be switched off through serial bus control to reduce power consumption. Both outputs of unused DACs should be connected to ground through a resister to avoid charge buildup. This document contains information on a new product. Specifications and information herein are subject to change without notice. No. 11 MC44724/5 Rev 0.21 03/25/97 ...
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... This document contains information on a new product. Specifications and information herein are subject to change without notice. 340 290 212 162 82 32 670 620 540 490 412 362 282 232 670 620 540 490 412 362 282 232 12 No. code 1023 232 0 code 1023 232 0 MC44724/5 Rev 0.21 03/25/97 ...
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... Digital Cb-input code(16~240) 525/60 and 625/50 system 100%amplitude,100%saturation color bar Å }30 Å }32 Å }30 Å }32 Å }22 Å }22 Å }30 Å }30 Å }32 Å }32 Å }22 Å }22 No. 13 480 404 332 256 180 108 code 1023 511 0 code 1023 511 0 MC44724/5 Rev 0.21 03/25/97 ...
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... Analog G output level(525/60 system) 100%amplitude,100%saturation color bar 670 232 200 12 Analog B output level(525/60 system) 100%amplitude,100%saturation color bar 1.371 (Cr-128 0.698 (Cr - 128) - 0.336 (Cb - 128 +1.732 (Cb - 128) No. 14 code 1023 0 code 1023 0 code 1023 0 MC44724/5 Rev 0.21 03/25/97 ...
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... Analog G output level(625/50 system) 100%amplitude,100%saturation color bar 670 232 44 Analog B output level(625/50 system) 100%amplitude,100%saturation color bar 1.371 (Cr-128 0.698 (Cr - 128) - 0.336 (Cb - 128 +1.732 (Cb - 128) No. 15 code 1023 0 code 1023 0 code 1023 0 MC44724/5 Rev 0.21 03/25/97 ...
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... WSS identification signals also identify and control the TV screen presentation mode - wide screen, letterbox and or normal -16:9 or 4:3. (see figures19 for sub-address register descriptions.) This document contains information on a new product. Specifications and information herein are subject to change without notice. No. 16 MC44724/5 Rev 0.21 03/25/97 ...
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... If your customer would NOT like to use this feature or customer do NOT have an agreement of the copy protection with MACROVISION, and then you should recommend the MC44723FT (no copy guard part). This document contains information on a new product. Specifications and information herein are subject to change without notice No copy MC44724/5 Rev 0.21 03/25/97 ...
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... D7 D6 LSB MSB ACK by MCU No LSB Sub-address LSB ACK LSB ACK Sub-address LSB ACK by MCU Data LSB Data N ACK by MCU MC44724/5 Rev 0.21 03/25/97 ACK Stop Stop Stop ...
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... This document contains information on a new product. Specifications and information herein are subject to change without notice LSB MSB LSB MSB LSB MSB LSB MSB Data N No LSB LSB Sub-address LSB LSB MC44724/5 Rev 0.21 03/25/97 ...
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... LSB MSB LSB MSB 20 No LSB LSB Sub-address Stop LSB LSB Data LSB LSB Data N Stop MC44724/5 Rev 0.21 03/25/97 ...
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... LSB Vyo 0.85 1.00 1.15 Vp-p Vyfs 0.85 1.00 1.15 V Vyzs - 0.0 0 120 - É ∂ L Symbol Min Typ Max Unit - - - 10 Bit INL - - Å }4.0 LSB Å }2.0 LSB DNL - - Vyo - 1.5 2.0 Vp-p Vyfs - 1.5 2.0 V Vyzs - 0.0 0.1 V É ∂ 240 - L No. 21 Other Vref = 1.1V Vref = 1.1V Vref = 1.5V Other Vref = 1.5V Vref = 1.5V Vref = 2V Vref = 2V MC44724/5 Rev 0.21 03/25/97 ...
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... Symbol Å @Min Typ 0.8 ILM V 2 IHM Å }10 É 0 50Å 50Å Tdh Tds Tr valid not valid No. 22 Unit MHz Å ì Unit É A É Max Unit MC44724/5 Rev 0.21 03/25/97 ...
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... DATA byte of Register (address auto-increment) AM Acknowledge, generated by the micro controller P Stop condition (When Last AM must be '1' ) This document contains information on a new product. Specifications and information herein are subject to change without notice. DATA 0 -------- A A DATA Slave receiver P Slave transmitter No. 23 MC44724/5 Rev 0.21 03/25/97 ...
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... DATA byte of Register (address auto-increment) P Chip select off (Lo to Hi) This document contains information on a new product. Specifications and information herein are subject to change without notice. DATA 0 -------- Sub Address N P Slave receiver --------- DATA No. 24 DATA N P Slave transmitter P MC44724/5 Rev 0.21 03/25/97 ...
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... VBI information data in vertical blanking period 0 : Frame sync output (default compsite sync output 0 : Vertical sync output (default Frame sync output 00 : 656 slave or H/V master mode 01 : 656 slave mode(no H/Vsync output) (defalt Fsync/Hsync slave mode 11 : Vsync/Hsync slave mode No. 25 LSB F/Vsync M/S M/S SW mode1 mode0 MC44724/5 Rev 0.21 03/25/97 ...
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... Note : this h-delay can be also related with 7A[7:0] register and can delay totally +2023 clock delay in H/V or H/Fsynnc slave mode. This document contains information on a new product. Specifications and information herein are subject to change without notice. h-polarity v-polarity f-polarity h- delay2 h-delay1 h-delay0 26 No. LSB MC44724/5 Rev 0.21 03/25/97 ...
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... On (need to set color bar mode on sub-address 70[5 setup level for luminunce = 0IRE 1 : setup level for luminunce = 7.5IRE 0 : 525 lines / 60 Hz mode 1 : 625 lines / 50 Hz mode 00 : NTSC( PAL (BDGHI PAL ( PAL (N) 27 No. LSB PAL/ PAL/ 625/525 NTSC1 NTSC2 MC44724/5 Rev 0.21 03/25/97 ...
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... Sub-address 75: Vertical Blanking Information Chroma (V) Level (write only) MSB Register default : 128(dec) (NTSC) This document contains information on a new product. Specifications and information herein are subject to change without notice 157(dec) (PAL 107(dec) (PAL) No. 28 LSB LSB LSB MC44724/5 Rev 0.21 03/25/97 ...
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... D/A converter (2) output On-Off control 0 : CVBS/Cb/BDAC2, C/Cr/RDAC2, Y/GDAC2 output On (default CVBS/Cb/BDAC2, C/Cr/RDAC2, Y/GDAC2 output Off : 17~25-pin's D/A converter (2) output signal control R/G/B output On (default Y/Cr/Cb output Y/C/CVBS output On 29 No. LSB dac sw1 dac sw0 Y dac LSB dac sw3 G dac dac sw4 MC44724/5 Rev 0.21 03/25/97 ...
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... H-delay6 H-delay5 H-delay4 H-delay3 0000_0000_000 : Hsync delay 0 delay to 1111_1111_000 : Hsync delay +255 delay delay totally +2023 delay(1111_1111_111 Fsync slave mode. 30 No. LSB sc-ph4 sc-ph3 sc-ph2 LSB - sc-ph1 sc-ph0 LSB MC44724/5 Rev 0.21 03/25/97 ...
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... Cr clock delay +1 clock clock delay +2 clock clock delay +3 clock clock delay 0 clock (default clock delay +1 clock 0 : 8-bit CbYCrY Digital Video Input mode (default 16-bit CbYCrY Digital Video Input mode No. 31 LSB 16-bit Y_tmg input mode MC44724/5 Rev 0.21 03/25/97 ...
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... CGMS data CGMS data off 0 : CGMS data CGMS data off 0 : RGB bf data RGB bf data off 0 : Cb/Cr bf data Cb/Cr bf data off 0 : Croma bf data Croma bf data off V-delay5 V-delay4 V-delay3 V-delay2 - - - - No. 32 LSB CbCr bf croma bf LSB LSB - V-delay1 V-delay0 MC44724/5 Rev 0.21 03/25/97 ...
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... Vsync with reference to DVIN data in slave mode V-delay8 0000_0000_000 : Vsync delay 0 delay V-delay7 to V-delay6 1111_1111_111 : Hsync delay +1023 delay V-delay5 V-delay4 V-delay3 V-delay2 V-delay1 V-delay0 This document contains information on a new product. Specifications and information herein are subject to change without notice. No. 33 MC44724/5 Rev 0.21 03/25/97 ...
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... LSB vid123 vid122 vid121 b9 b11 b10 LSB vid133 vid132 vid131 b19 b18 b17 b12 b14 b16 b18 b20 b13 b15 b17 b19 b11 PAL only LSB wss2 wss1 wss0 LSB wss10 wss9 wss8 b9 b11 b10 500mV +-5% MC44724/5 Rev 0.21 03/25/97 ...
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... Fig 20 : Closed caption wave form Field 2 No. 35 LSB ccb113 ccb112 ccb111 LSB ccb123 ccb122 ccb121 LSB ccb213 ccb212 ccb211 LSB ccb223 ccb222 ccb221 50IRE 0IRE MC44724/5 Rev 0.21 03/25/97 ...
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... CGMS information data insertion Off 1 : CGMS information data insertion closed caption/extended data for field2 encoding Off 1 : closed caption/extended data for field2 encoding closed caption/extended data for field1 encoding Off 1 : closed caption/extended data for field1 encoding On No. 36 LSB CGMS CC2 CC1 MC44724/5 Rev 0.21 03/25/97 ...
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... Closed Caption Status Flag for field2 [5] Automatic set to null code(Closed Caption data) [4] n.a. [3] WSS information data insetion on/off (default 0: off) [2] CGMS on/off (default 0: off) [1] CC closed caption/extended data for field2 encoding (default 0: off) [0] CC closed caption/extended data for field1 encoding (default 0: off) 37 No. MC44724/5 Rev 0.21 03/25/97 ...
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... DAVdd 14 VReff2 Ibias2 No PEG EXT 48 TVIN 47 DECODER DVIN0 46 DVIN1 45 DVIN2 44 DVIN3 43 DVIN4 42 DVIN5 41 DVIN6 40 DVIN7 39 DVss 38 DVdd 37 SEL 36 SCL/SCK 35 SDA/ NTSC " PAL " MC44724/5 Rev 0.21 03/25/97 ...
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... This document contains information on a new product. Specifications and information herein are subject to change without notice Detail É No min max - 1.70 0.05 0.15 1.40TYP 0.18 0.27 0.10 0.20 9.90 10.1 9.90 10.1 0.50 11.80 12.20 11.80 12.20 0.50TYP 0.80 1. 0.10 1.25TYP 1.25TYP MC44724/5 Rev 0.21 03/25/97 ...