TEA5768HL/V2 STEricsson, TEA5768HL/V2 Datasheet - Page 9

• Manufacturer Part Number: TEA5768HL/V2
• Manufacturer: STEricsson

Specifications of TEA5768HL/V2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
Table 7.
[1]
Table 8.
[1]
SAA7133HL_2
Product data sheet
Symbol
GPIO27
GPIO26
GPIO25
V_CLK
GPIO23
GPIO22
GPIO21
GPIO20
GPIO19
GPIO18
GPIO17
GPIO16
GPIO15 to
GPIO8
GPIO7 to
GPIO0
Symbol
INT_A
PERR#
SERR#
PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements
The SAA7133HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions can be selected:
a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601); zoom-video, with discrete sync
b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder; synchronized by Start Of Packet (SOP); in
c) Digitized raw DTV/DVB samples stream output: from internal ADCs; to feed the peripheral DTV/DVB channel decoder.
d) Program Stream (PS) capture input, e.g. from an external MPEG encoder chip.
e) GPIO: as default (no other function selected); static (no clock); read and write from or to individually selectable pins; latching ‘strap’
f) Use an external 4.7 k pull-up resistor at GPIO16 for an external 24.576 MHz crystal; due to an internal pull-down resistor, an
g) Peripheral interrupt (INT) input: enabled by interrupt enable register; routed to PCI interrupt (INT_A).
signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes.
byte-parallel or bit-serial protocol.
information at system reset time.
open-circuit GPIO16 pin requires an external 32.11 MHz crystal.
Pin
87
88
89
66
56
57
58
59
60
61
67
68
69 to 72
and
75 to 78
79 to 86
PCI interface pins
GPIO pins and functions
Pin
126
30
31
Type Function
GIO
GIO
GIO
GO
GIO
GIO
GIO
GIO
GIO
GIO
GIO
GIO
GIO
GIO
Type
PO and O/D
PIO and S/T/S parity error input or output: the receiving device detects data parity error (active
PO and O/D
Audio and video port outputs
A_SDO (I
A_WS (I
A_SCK (I
V_CLK (also gated)
HSYNC
VSYNC
-
-
-
VAUX2; A_CLK_master,
A_REF_CLK
VAUX1 (e.g. VACTIVE);
A_SDO_aux, I
-
VP[7:0] for formats: ITU-R BT.656,
VMI, VIP (1.1, 2.0), etc.
VP extension for 16-bit formats:
ZV, VIP-2, DMSD, etc.
…continued
2
S-bus word select)
2
2
[1]
S-bus clock)
S-bus 1 data)
Description
interrupt A output: this pin is an open-drain interrupt output, conditions assigned by
the interrupt register
LOW)
system error output: reports address parity error (active LOW)
[1]
2
S-bus 2 data
Rev. 02 — 18 February 2008
TS and PS capture inputs
-
-
-
-
-
TS_LOCK (channel decoder
locked)
TS_S_D (bit-serial data)
TS_CLK (< 33 MHz)
TS_SOP (packet start)
-
-
TS_VAL (valid flag)
-
TS_P_D[7:0] (transport
stream or program stream,
byte-parallel data)
PCI audio and video broadcast decoder
Raw DTV/DVB
outputs
-
-
ADC_CLK (out)
ADC_C[0] (LSB) R/W, INT
-
-
-
-
X_CLK_IN
ADC_Y[0] (LSB) R/W
-
ADC_Y[8:1]
ADC_C[8:1]
-
SAA7133HL
© NXP B.V. 2008. All rights reserved.
GPIO
R/W
R/W
R/W
-
R/W, INT
R/W
R/W
R/W
R/W, INT
R/W, INT
R/W
R/W
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