TEA5768HL/V2 STEricsson, TEA5768HL/V2 Datasheet - Page 33

• Manufacturer Part Number: TEA5768HL/V2
• Manufacturer: STEricsson

Specifications of TEA5768HL/V2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

NXP Semiconductors
SAA7133HL_2
Product data sheet
6.9.2 Propagate reset
6.9.3 GPIO
The I
allows application of the device in the stand-alone mode, i.e. with the PCI-bus not
connected. Under the slave mode, all internal programming registers can be reached via
the I
The PCI system reset and ACPI power management state D3 is propagated to peripheral
devices by the dedicated pin PROP_RST. This signal is switched to active LOW by reset
and D3, and is only switched HIGH under control of the device driver ‘by will’. The
intention is that peripheral devices will use signal PROP_RST as Chip-Enable (CE). The
peripheral devices should enter a low power consumption state if pin PROP_RST = LOW,
and reset into default setting at the rising edge.
The SAA7133HL offers a set of General Purpose Input/Output (GPIO) pins, to interface to
on-board peripheral circuits; see also
dedicated functions:
Any GPIO pin that is not used for a dedicated function is available for direct read and write
access via the PCI-bus. Any GPIO pin can be selected individually as input or output
(masked write). By these means, very tailored interfacing to peripheral devices can be
created via the SAA7133HL capture driver running on Windows operating systems.
At system reset (PCI reset) all GPIO pins will be set to 3-state and input, and the logic
level present on the GPIO pins at that moment will be saved into a special ‘strap’ register.
All GPIO pins have an internal pull-down resistor (LOW level), but can be strapped
externally with a 4.7 k resistor to the supply voltage (HIGH level). The device driver can
investigate the strap register for information about the hardware configuration of a given
board.
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Digital video port output: 8-bit or 16-bit wide (including raw DTV)
Digital audio serial output: i.e. I
Transport stream input:
– parallel (also applicable for program stream and elementary stream)
– serial (also applicable as I
Peripheral interrupt input: four GPIO pins of the SAA7133HL can be enabled to raise
an interrupt on the PCI-bus; by this means, peripheral devices can directly intercept
with the device driver on changed status or error conditions
2
2
C-bus with exception of the PCI configuration space.
C-bus interface is multi-master capable and can assume slave operation too. This
Rev. 02 — 18 February 2008
2
S-bus input)
2
S-bus output
Table
8. These GPIOs are intended to take over
PCI audio and video broadcast decoder
SAA7133HL
© NXP B.V. 2008. All rights reserved.
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