SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 16

• Manufacturer Part Number: SSTUA32866EC/G-T
• Manufacturer: NXP Semiconductors

Specifications of SSTUA32866EC/G-T

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 2V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
11. Test information
SSTUA32866_2
Product data sheet
11.1 Parameter measurement information for data output load circuit
V
All input pulses are supplied by generators having the following characteristics:
PRR
The outputs are measured one at a time with one transition per measurement.
Fig 10. Load circuit, data output measurements
Fig 11. Voltage and current waveforms; inputs active and inactive times
Fig 12. Voltage waveforms; pulse duration
DD
= 1.8 V
(1) C
(1) I
CK inputs
10 MHz; Z
V
V
V
DD
ID
IH
IL
L
includes probe and jig capacitance.
= V
tested with clock and data inputs held at V
= 600 mV
= V
ref
0.1 V.
ref
+ 250 mV (AC voltage levels) for differential inputs. V
R L = 100
test point
test point
0
250 mV (AC voltage levels) for differential inputs. V
RESET
= 50 ; input slew rate = 1 V/ns
input
LVCMOS
50
Rev. 02 — 26 March 2007
I
DD
1.8 V DDR2-667 configurable registered buffer with parity
(1)
0.5V
t
INACT
DD
V
10 %
ICR
CK
CK
DUT
OUT
t
W
DD
or GND, and I
20 %, unless otherwise specified.
delay = 350 ps
Z o = 50
0.5V
V
ICR
t
IL
IH
ACT
O
DD
= GND for LVCMOS inputs.
= 0 mA.
= V
C L = 30 pF (1)
SSTUA32866
002aaa373
V
0 V
DD
DD
V
002aaa372
ID
for LVCMOS inputs.
90 %
V
V
IH
IL
© NXP B.V. 2007. All rights reserved.
V
DD
R L = 1000
R L = 1000
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