CP3BT26G18NEP/HAPB National Semiconductor, CP3BT26G18NEP/HAPB Datasheet - Page 87

• Manufacturer Part Number: CP3BT26G18NEP/HAPB
• Manufacturer: National Semiconductor

Specifications of CP3BT26G18NEP/HAPB

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

PREF_CFG The Positive Voltage Reference Configuration
NREF_CFG The Negative Voltage Reference Configura-
MUXOUTEN The MUXOUT Enable bit controls whether the
INTEN
field specifies the source of the ADC positive
voltage reference, according to the following
table:
tion field specifies the source of the ADC neg-
ative voltage reference, according to the
following table:
output of the Input Multiplexer is available ex-
ternally.
MUXOUT0 pin is active and the MUXOUT1
pin is disabled (TRI-STATE). In differential
mode, both MUXOUT0 and MUXOUT1 are
active.
0 – MUXOUT0 and MUXOUT1 disabled.
1 – MUXOUT0 and MUXOUT1 enabled.
The Interrupt Enable bit controls whether the
ADC interrupt (IRQ13) is enabled. When en-
abled, the interrupt request is asserted when
valid data is available in the ADCRESLT reg-
ister. This bit has no effect on the wake_up
signal to the MIWU unit (WUI30).
0 – IRQ13 disabled.
1 – IRQ13 enabled.
PREF_CFG
NREF_CFG
00
01
10
11
00
01
10
11
In
single-ended
Internal (AGND)
Internal (AVCC)
PREF Source
NREF source
Reserved
VREFP
ADC0
ADC1
ADC2
ADC3
mode,
the
87
16.5.2
The ADCACR register is used to control the clock configu-
ration and report the status of the ADC module. The CPU
bus master has read/write access to the ADCACR register.
After reset, this register is clear.
CLKSEL
CLKDIV
PRM
TRG
CNVT
CNVT TRG
15
ADC Auxiliary Configuration Register
(ADCACR)
14
The Clock Select bit selects the clock source
used by the DELAY2 block to generate the
ADC clock.
0 – ADC clock derived from System Clock.
1 – ADC clock derived from Auxiliary Clock 2.
The Clock Divisor field specifies the divisor
applied to System Clock to generate the 12
MHz clock required by the ADC module. Only
the System Clock is affected by this divisor.
The divisor is not used when Auxiliary Clock 2
is selected as the clock source.
The ADC Primed bit is a read-only bit that in-
dicates the ADC has been primed to perform
a conversion by writing to the ADCSTART reg-
ister. The bit is cleared after the conversion is
completed.
0 – ADC has not been primed.
1 – ADC has been primed.
The ADC Triggered bit is a read-only bit that
indicates the ADC has been triggered. The bit
is set during any pre-conversion delay. The bit
is cleared after the conversion is completed.
0 – ADC has not been triggered.
1 – ADC has been triggered.
The ADC Conversion bit is a read-only bit that
indicates the ADC has been primed to per-
form a conversion, a valid internal or external
trigger event has occurred, any pre-conver-
sion delay has expired, and the ADC conver-
sion is in progress. The bit is cleared after the
conversion is completed.
0 – ADC is not performing a conversion.
1 – ADC conversion is in progress.
PRM
13
CLKDIV
00
01
10
11
12
Reserved
3
Clock Divisor
CLKDIV CLKSEL
2
Reserved
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1
2
4
1
0