CP3BT26G18NEP/HAPB National Semiconductor, CP3BT26G18NEP/HAPB Datasheet - Page 86

• Manufacturer Part Number: CP3BT26G18NEP/HAPB
• Manufacturer: National Semiconductor

Specifications of CP3BT26G18NEP/HAPB

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: LQFP
• Lead Free Status / RoHS Status: Not Compliant

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16.5.1
The ADCGCR register controls the basic operation of the in-
terface. The CPU bus master has read/write access to the
ADCGCR register. After reset this register is set to 0000h.
CLKEN
ADCIN
DIFF
MUXOUTEN INTEN Res.
TOUCH_CFG
8
TOUCH_CFG
15
11X
000
001
010
011
100
101
7
ADC Global Configuration Register (ADCGCR)
The Clock Enable bit controls whether the
ADC module is running. When this bit is clear,
all ADC clocks are disabled, the ADC analog
circuits are in a low-power state, and ADC
registers (other than the ADCGCR and AG-
CACR registers) are not writeable. Clearing
this bit reinitializes the ADC state machine
and cancels any pending trigger event. When
this bit is set, the ADC clocks are enabled and
the ADC analog circuits are powered up. The
converter is operational within 0.25 µs of be-
ing enabled.
0 – ADC disabled.
1 – ADC enabled.
The ADCIN bit selects the source of the ADC
input. When the bit is clear, the source is the
8-channel Input Multiplexer. When the bit is
set, the source is the ADCIN pin.
0 – ADC input is from 8-channel multiplexer.
1 – ADC input is from ADCIN pin.
The Differential Operation Mode bit and the
MUX_CFG field configure the analog circuits
of the ADC module. When this bit is clear, the
ADC module operates in single-ended mode.
When this bit is set, the ADC operates in dif-
ferential mode. See Table 35 .
0 – Single-ended mode.
1 – Differential mode.
6
14
5
MUX_CFG
Weakly Pulled High
13
ADC0/TSX+
Driven High
Driven High
4
Inactive
Inactive
Inactive
Inactive
NREF_CFG
3
12
DIFF ADCIN CLKEN
2
11
Table 36 TOUCH_CFG Modes
1
PREF_CFG
ADC1/TSY+
Driven High
Driven High
10
Inactive
Inactive
Inactive
Inactive
Inactive
0
9
86
MUX_CFG
TOUCH_CFG The Touchscreen Configuration field controls
ADC2/TSX-
Driven Low
Driven Low
Inactive
Inactive
Inactive
Inactive
Inactive
The Multiplexer Configuration field and the
DIFF bit configure the analog circuits of the
ADC module, as shown in Table 35.
For best noise immunity in touchscreen appli-
cations, channel 2 should be used for sam-
pling the X plate voltage, and channel 1
should be used for sampling the Y plate volt-
age.
the configuration of the low-ohmic drivers for
the TSX+, TSX-, TSY+, and TSY- signals, as
shown in Table 36. When TOUCH_CFG is
101b, the pen-down detector is enabled. The
output of the pen-down detector is visible to
software in the PEN_DOWN bit of the AD-
SRESLT register, and it is ORed with the
Done signal to generate the wake-up signal
WUI30 passed to the MIWU unit.
MUX_CFG
Table 35 MUX_CFG Operation
000
001
010
011
100
101
110
111
ADC3/TSY-
Driven Low
Driven Low
Driven Low
Inactive
Inactive
Inactive
inactive
(DIFF = 0)
Selected,
Channel
0
1
2
3
4
5
6
7
Pen-Down Detect
Pre-Pen Down
Sample Z (1),
Sample Z (2)
Sample Y
Sample X
Reserved
Mode
None
Channels
(DIFF = 1)
Selected
+
0
1
2
3
4
5
6
7
1
0
3
2
5
4
7
6
-