STA320 STMicroelectronics, STA320 Datasheet

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... Internal Processing Sample Rate ■ 28-bit precision 2 DESCRIPTION The STA320 is a single chip solution for digital audio processing and control in 2.1-channel applications. It provides output capabilities for DDX Amplification). In conjunction with a DDX device, it provides high-quality, high-efficiency, all digital amplification. STA320 ...

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... STA320 Figure 2. PIN CONNECTION (Top view) RESERVED FILTER_PLL Table 2. ABSOLUTE MAXIMUM RATINGS Symbol V 3.3V I/O Power Supply DD V 3.3V Logic Power Supply DDA V Voltage on input pins i V Voltage on output pins o T Storage Temperature stg T Ambient Operating Temperature amb Table 3. THERMAL DATA ...

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... Over-current Indicator I Power Fault Indicator I Thermal Warning Indicator Digital Ground STA320 Pad Type CMOS Input Buffer with Pull-Down 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer 3.3V Capable TTL 4mA Output Buffer ...

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... The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA320 is always a slave device in all of its communications. It supported up to 400KB/sec rate (fast-mode bit rate). ...

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... RW, this bit is set read mode and 0 for write mode and 0 for write mode. After a START condition the STA320 identifies on the bus the device address and if a match is found, it acknowledges the identification on SDA bus during the 9 identification byte is the internal space address ...

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... STA320 Figure 4. Read Mode Sequence ACK CURRENT DEV-ADDR ADDRESS READ START RW ACK RANDOM DEV-ADDR ADDRESS READ START RW RW= ACK HIGH SEQUENTIAL DEV-ADDR CURRENT READ START ACK SEQUENTIAL DEV-ADDR RANDOM READ START RW 5 REGISTER SUMMARY Table 8. Register Summary Addr Name D7 0x00 ConfA ...

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... R R/W 0 The STA320 will support sample rates of 32kHz, 44.1kHz, 48Khz, 88.2kHz, 96kHz, Therefore the internal clock will be: – 32.768Mhz for 32kHz – 45.1584Mhz for 44.1khz, 88.2kHz and 176.4kHz – 49.152Mhz for 48kHz, 96kHz, and 192kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency(fs). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (Input Rate) register bits ...

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... R/W 00 The STA320 has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through). or provides a 2 times downsample. The IR bits determine the oversampling ratio of this interpolation. ...

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... The STA320 audio serial input was designed to interface with standard digital audio components and to accept a number of serial data formats. STA320 always acts a slave when receiving audio input from stan- dard digital audio components. Serial data for two channels is provided using 3 inputs: left/right clock LRC- KI, serial clock BICKI, and serial data 1 & ...

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... STA320 For example, SAI=1110 and SAIFB=1 would specify Right-Justified 16-bit data, LSB-First. Table 4 below lists the serial audio input formats supported by STA320 as related to BICKI = 32/48/64fs, where sampling rate fs = 32/44.1/48/88.2/96kHz. Table 12. Supported Serial Audio Input Formats BICKI SAI (3...0) 32fs 48fs 64fs 5 ...

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... OM1 NAME CSZ0 Contra Size Register: When OM(1,0) = 11, this register determines the size of the DDX compensating pulse from 0 CSZ1 clock ticks to 31 clock periods. CSZ2 CSZ3 CSZ4 Compensating Pulse Size STA320 DESCRIPTION 2 S Input 2 S Input 2 S Input 2 S Input D2 D1 ...

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... R/W RST 0 R/W 0 The STA320 features an internal digital high-pass filter for the purpose of AC coupling. The purpose of this filter is to prevent DC signals from passing through a DDX amplifier. DC signals can cause speaker damage. When HPB=0, this filter is enabled 5.4.2 De-Emphasis BIT R/W ...

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... NAME MPCV Max Power Correction Variable Use Standard MPC Coefficient 1 - Use MPCC bits for MPC Coefficient NAME MPC Max Power Correction: Setting of 1 enables STA50x/STA51x correction for THD reduction near maximum power output STA320 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION NSBW MPC MPCV ...

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... R/W 0 The STA320 features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to ~83dB in this mode, which is still greater than the SNR of AM radio ...

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... S data and will automatically mute if the sig- NAME BCLE Binary Output Mode Clock Loss Detection Enable NAME LDTE LRCLK Double Trigger Protection Enable NAME ECLE Auto EAPD on Clock Loss STA320 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 15/37 ...

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... STA320 5.6.6 IC Power Down BIT R/W RST 7 R/W 1 The PWDN register is used to place the low-power state. When PWDN is written as 0, the output will begin a soft-mute. After the mute condition is reached, EAPD will be asserted to power down the power-stage, then the mas- ter clock to all internal hardware expect the I consumption stateConf 5 ...

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... C3V6 0 1 The Volume structure of the STA320 consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5dB steps from +48dB to -80 dB example if C3V = 00h or +48dB and MV = 18h or -12dB, then the total gain for channel 3 = +36dB. ...

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... STA320 Table 17. Channel Volume as a function of CxV(7..0) CxV(7..0) 00000000(00h) 00000001(01h) 00000010(02h) … 01100001(5Fh) 01100000(60h) 01011111(61h) … 11010111(D7h) 11011000(D8h) 11011001(D9h) 11011010(DAh) … 11101100(ECh) 11101101(EDh) … 11111111(FFh) 5.8 Auto Mode Registers 5.8.1 AutoMode Register 1(Address 0x0B AMPS AMGC1 1 Table 18. AutoMode EQ Settings AMEQ(1,0) 00 User Programmable 01 Preset EQ – ...

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... XO2 XO3 Mode DESCRIPTION D2 D1 AMAM1 AMAM0 0 0 DESCRIPTION 44.1kHz/88.2kHz Input Fs 0.535MHz – 0.670Mhz 0.671MHz – 0.800MHz 0.801MHz – 1.000MHz 1.001MHz – 1.180MHz 1.181MHz – 1.340Mhz 1.341MHz – 1.500MHz 1.501MHz – 1.700MHz DESCRIPTION STA320 D0 AMAME 0 19/37 ...

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... STA320 Table 22. Bass Management Crossover Frequency XO3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 5.8.6 AutoModeRegister 3 (address 0x0D Table 23. Preset EQ Settings PEQ(3..0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 ...

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... B is negative inverse. CxBO DDX tri-state output - normal operation 1 - Binary OutputLimiter Select Limiter Selection can be made on a per-channel basis according to the channel limiter select bits C1LS0 C1BO C2LS0 C2BO C3LS0 C2BO STA320 C1VPB C1EQBP C1TCB C2VPB C2EQBP C2TCB C3VPB 0 21/37 ...

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... STA320 Table 24. Channel Limiter Mapping as a function of CxLS bits CxLS(1, 5.9.8 Output Mapping Output mapping can be performed on a per channel basis according to the CxOM channel output mapping bits. Each input into the output configuration engine can receive data from any of the three processing channel outputs ...

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... DDX amplifier. Since gain can be added digitally within the STA320 it is possible to exceed 0dBFS or any other LxAT setting, when this occurs, the limiter, when active, will automatically start reducing the gain. The rate at which the gain is reduced when the attack threshold is exceeded is dependent upon the attack rate reg- ister setting for that limiter ...

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... STA320 Table 26. Limiter Attack Rate as a function of LxA bits. LxA(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 27. Limiter Release Rate as a function of LxR bits. LxR(3..0) 0000 0001 0010 0011 0100 0101 ...

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... AC(dB relative to FS) -12 - +10 AC(dB relative to FS) -∞ -29dB -20dB -16dB -14dB -12dB -10dB -8dB -7dB -6dB -5dB -4dB -3dB -2dB -1dB -0dB STA320 25/37 ...

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... STA320 5.13 Dynamic Range Compression Mode Table 30. Limiter Attack Threshold as a function of LxAT bits (DRC-Mode). LxAT(3..0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 31. Limiter Release Threshold function of LxRT bits (DRC-Mode). LxRT(3..0) ...

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... D4 D3 C1B13 C1B12 C1B11 C1B5 C1B4 C1B3 C2B20 C2B19 C2B13 C2B12 C2B11 C2B5 C2B4 C2B3 C1B20 C1B19 C3B13 C3B12 C3B11 STA320 CFA2 CFA1 CFA0 C1B18 C1B17 C1B16 C1B10 C1B9 C1B8 C1B2 C1B1 C1B0 C2B18 C2B17 C2B16 C2B10 C2B9 C2B8 C2B2 C2B1 ...

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... Write Control Register D7 D6 Coefficients for user-defined EQ, Mixing, Scaling, and Bass Management are handled internally in the STA320 via RAM. Access to this RAM is available to the user via an I are dedicated to this function. One contains a coefficient base address, five sets of three store the values of the 24-bit coefficients to be written or that were read, and one contains bits used to control the write/read of the coefficient(s) to/from RAM ...

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... C address 20h 2 C address 21h 2 C address 22h 2 C address 23h 2 C address 15h 2 C address 16h 2 C address 17h 2 C register 14h 2 C address 15h 2 C address 16h 2 C address 17h 2 C address 18h 2 C address 19h STA320 29/37 ...

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... STA320 will generate the RAM addresses as offsets from this base value to write the complete set of coefficient data. 5.14.22User-Defined EQ The STA320 provides the ability to specify four EQ filters (biquads) per each of the two input channels. The bi- quads use the following equation: Y[n] = 2(b ...

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... By default, all user-defined filters are "pass-thru" where all coefficients are set to 0, except the b0/2 coefficient which is set to 400000h (representing 0.5) 5.14.23Pre-Scale The STA320 provides a multiplication for each input channel for the purpose of scaling the input prior to EQ. This pre-EQ scaling is accomplished by using a 24-bit signed fractional multiplier, with 800000h = -1 and 7FFFFFh = 0.9999998808. ...

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... STA320 Table 32. RAM Block for Biquads, Mixing, and Bass Management Index Index (Decimal) (Hex) 0 00h 1 01h 2 02h 3 03h 4 04h 5 05h … … 19 13h 20 14h 21 15h … … 39 27h 40 28h 41 29h 42 2Ah 43 2Bh 44 2Ch 45 2Dh 46 2Eh 47 2Fh 48 30h 49 31h 50 32h 51 33h 52 34h ...

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... Reserved Registers(Addresses 30h-31h RES RES MPCC12 MPCC11 MPCC4 MPCC3 FDRC12 FDRC11 FDRC4 FDRC3 OCWARN RES RES RES RES RES RES STA320 MPCC10 MPCC9 MPCC8 MPCC2 MPCC1 MPCC0 FDRC10 FDRC9 FDRC8 FDRC2 FDRC1 FDRC0 TFAULT FAULT TWARN RES RES RES RES ...

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... STA320 5.19 RES RES For details see next AN. 34/ RES RES RES RES RES RES ...

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... L 0.4 1.27 S inch MIN. TYP. MAX. 0.104 0.3 0.004 0.012 0.014 0.019 0.009 0.013 0.020 45° (typ.) 0.697 0.713 0.394 0.419 0.050 0.65 7.6 0.291 0.299 0.016 0.050 8 ° (max.) ® packages. These OUTLINE AND MECHANICAL DATA SO-28 STA320 35/37 ...

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... STA320 Table 33. Revision History Date Revision November 2004 36/37 1 First Issue Description of Changes ...

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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America All other names are the property of their respective owners DDX is a trademark of Apogee tecnology inc. © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STA320 37/37 ...