MC9328MXSCVP10R2 Freescale, MC9328MXSCVP10R2 Datasheet

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... It is packaged in a 225-contact MAPBGA package. Figure 1 shows the functional block diagram of the i.MXS processor. Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2006. All rights reserved. Document Number: MC9328MXS Rev. 3, 12/2006 ...

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... Pulse-Width Modulation (PWM) Module • Universal Serial Bus (USB) Device • Direct Memory Access Controller (DMAC) • Synchronous Serial Interface and an Inter-IC Sound (SSI/I 2 • Inter- Bus Module • General-Purpose I/O (GPIO) Ports • Bootstrap Mode Module MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor ...

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... LSB means least significant bit or bits, and MSB means most significant bit or bits. References to low and high bytes or words are spelled out. • Numbers preceded by a percent sign (%) are binary. Numbers preceded by a dollar sign ($) or 0x are hexadecimal. Freescale Semiconductor Table 1. i.MXS Ordering Information Temperature Solderball Type O ...

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... DQM [3:0] SDRAM data enable CSD0 SDRAM Chip-select signal which is multiplexed with the CS2 signal. These two signals are selectable by programming the system control register. 4 Table 2. i.MXS Signal Descriptions Function/Notes External Bus/Chip-Select (EIM) Bootstrap SDRAM Controller MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor ...

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... driven logic-low at reset, the external chip-select space will be configured to little endian. This input must not change state after power-on reset negates or during chip operation. Freescale Semiconductor Function/Notes Clocks and Resets ...

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... Timer Input Capture or Timer Input Clock—The signal on this input is applied to both timers simultaneously. TMR2OUT Timer 2 Output USBD_VMO USB Minus Output USBD_VPO USB Plus Output USBD_VM USB Minus Input USBD_VP USB Plus Input 6 Function/Notes ETM LCD Controller SPI 1 General Purpose Timers USB Device MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor ...

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... I2C_SDA I C Data PWMO PWM Output TRISTATE Forces all I/O signals to high impedance for test purposes. For normal operation, terminate this input with ohm resistor to ground. (TRI-STATE PA[14:3] Dedicated GPIO Freescale Semiconductor Function/Notes UARTs – IrDA/Auto-Bauding 2 S protocol PWM Test Function ® ...

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... PA29 69K STAT1 I/O 69K O ETMPIPE O PA28 69K STAT0 I/O 69K O ETMTRAC O PA27 69K EPKT3 I/O 69K MC9328MXS Technical Data, Rev. 3 Table 6 on page 17 to configure the AIN BIN AOUT Default Reser A24 ved A23 A22 A21 A20 A19 Freescale Semiconductor ...

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... NVDD1 N3 D12 NVDD1 P3 A4 NVDD1 R2 D11 NVDD1 N4 EB0 NVDD1 M4 D10 NVDD1 P4 A3 NVDD1 R3 EB1 NVDD1 N5 D9 NVDD1 R4 EB2 Freescale Semiconductor Alternate GPIO Pull- Pull Dir Signal Dir Mux Up -Up O ETMTRAC O PA26 69K EPKT2 I/O 69K O ETMTRAC O PA25 69K EPKT1 I/O 69K ...

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... PA19 69K EPKT6 I/O 69K ETMTRAC PA18 69K EPKT5 I/O 69K ETMTRAC PA17 69K EPKT4 I/O 69K O O I/O 69K MC9328MXS Technical Data, Rev. 3 AIN BIN AOUT Default PA23 PA22 A0 CSD1 CSD0 ECB LBA BCLK Reser DTACK PA17 ved Freescale Semiconductor ...

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... NVDD2 K12 TDI NVDD2 J11 I2C_SCL NVDD2 H14 I2C_SDA NVDD2 H13 Reserved NVDD2 G14 Reserved NVDD2 H12 Reserved NVDD2 G13 Reserved NVDD2 J10 Reserved NVDD2 G15 Reserved Freescale Semiconductor Alternate GPIO Pull- Pull Dir Signal Dir Mux Static Static I 69K 69K O I ...

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... PA4 PA3 PA2 Reserved PA1 Reser PD31 ved PD30 PD29 PD28 PD27 PD26 PD25 PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 Reser PD10 ved Reserved PD9 Reser PD8 ved Reser PD7 ved Freescale Semiconductor ...

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... NVDD4 E7 UART2_R TS NVDD4 F7 UART2_C TS NVDD4 B6 USBD_VM O NVDD4 C6 USBD_VP O NVDD4 A6 USBD_VM NVDD4 D6 USBD_VP NVDD4 A5 USBD_SU SPND Freescale Semiconductor Alternate GPIO Pull- Pull Dir Signal Dir Mux Up -Up O PD6 69K I/O PC17 69K I/O PC16 69K I/O PC15 69K I/O PC14 69K I/O ...

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... Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static Static MC9328MXS Technical Data, Rev. 3 AIN BIN AOUT Default -Up PB22 PB21 PB20 PB19 PB18 PB17 PB16 PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 Freescale Semiconductor ...

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... Pull down this input with 1KΩ resistor to GND. 2 External circuit required to drive this input. 3 Tie this input high (to AVDD) or pull down with 1KΩ resistor to GND. 4 Pull up this output with a resistor to NVDD2. Freescale Semiconductor Alternate GPIO Pull- Pull Dir Signal Dir Mux ...

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... For more information about I/O pads grouping per VDD, please refer to 16 Table 4. Maximum Ratings Rating Minimum MC9328MXS Technical Data, Rev. 3 Maximum Unit -0.3 3.3 V -0.3 1.9 V -0.3 3.3 V -0.3 3.3 V – 2000 V – 100 V – 200 mA °C -55 150 800 1300 ® Table 2 on page 4. Freescale Semiconductor ...

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... Input high voltage IH V Input low voltage IL V Output high voltage ( Output low voltage (I = -2.5 mA Input low leakage current GND, no pull-up or pull-down) IN Freescale Semiconductor Rating Min ° C) ° C) ° C) ° C) 0.7V = 2.0 mA) 0.7V MC9328MXS Technical Data, Rev. 3 Electrical Characteristics Minimum Maximum Unit 0 70 ° ...

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... TBD TBD MC9328MXS Technical Data, Rev. 3 Typical Max Unit μA – ±1 – – mA – – mA μA – ±5 – – All L H Maximum Unit – 20.8 ns Maximum Unit – – ms TBD – – – – Freescale Semiconductor ...

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... Clock high time 2b Clock low time 3a Clock rise time 3b Clock fall time 4a Output hold time 4b Output setup time Freescale Semiconductor Functional Description and Application Information Figure 2. See Table 9 for the ETM9 timing parameters used Valid Data 4a Figure 2. Trace Port Timing Diagram 1.8 ± ...

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... T 300 (56 μs) ref 250 T 270 (50 μs) ref 350 T 400 (70 μs) ref 320 T 370 (64 μs) ref 0.005 2•T – 0.01 dck (0.01%) 1.0 – 1.5 ns (10%) – 2.5 V – – Figure 3 and Freescale Semiconductor ...

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... HRESET RESET_OUT CLK32 HCLK Figure 3. Timing Relationship with POR RESET_IN HRESET RESET_OUT 6 CLK32 HCLK Figure 4. Timing Relationship with RESET_IN Freescale Semiconductor Functional Description and Application Information 1 10% AVDD 2 Exact 300ms 3 5 MC9328MXS Technical Data, Rev cycles @ CLK32 4 14 cycles @ CLK32 14 cycles @ CLK32 ...

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... Table 12 22 1.8 ± 0.1 V Min Max 1 note 300 300 defines the parameters of signals. MC9328MXS Technical Data, Rev. 3 3.0 ± 0.3 V Unit Min Max – 1 – – note 300 300 Cycles of CLK32 Cycles of CLK32 – 4 – Cycles of CLK32 Cycles of CLK32 Freescale Semiconductor ...

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... Table 12. EIM Bus Timing Parameter Table Ref No. Parameter 1a Clock fall to address valid 1b Clock fall to address invalid 2a Clock fall to chip-select valid 2b Clock fall to chip-select invalid 3a Clock fall to Read (Write) Valid 3b Clock fall to Read (Write) Invalid Freescale Semiconductor Functional Description and Application Information ...

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... Freescale Semiconductor ...

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... OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when EBC bit in CS5L register is clear. 3. Address becomes valid and CS asserts at the start of read access cycle. 4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state. Freescale Semiconductor Functional Description and Application Information 2 9 ...

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... OE negate after EB negate 11 Wait becomes low after CS5 asserted Minimum See note 2 3T 1.5T-0.68 – – 2T+1.57 T-1.49 – T 0.06 0 MC9328MXS Technical Data, Rev 3.0 ± 0.3 V Unit Maximum – ns – ns 1.5T-0.06 ns 0.05 ns 1020T ns 3T+7.33 ns – – ns 0.18 ns 1019T ns Freescale Semiconductor ...

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... Number Characteristic 1 CS5 assertion time 2 EB assertion time 3 CS5 pulse width 4 RW negated before CS5 is negated 5 RW negated to Address inactive 6 Wait asserted after CS5 asserted Freescale Semiconductor Functional Description and Application Information Minimum Minimum See note 2 See note 2 3T 2.5T-3.63 64.22 – ...

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... WAIT Write Cycle DMA Enabled Address 1 programmable min 0ns CS5 2 programmable min 0ns (logic high) 12 WAIT 9 DATABUS S Figure 9. WAIT Write Cycle DMA Enabled 28 3.0 ± 0.3 V Minimum T+2.66 2T+0.03 – 0. MC9328MXS Technical Data, Rev. 3 Unit Maximum 2T+7.96 ns – 0.5T+0.5 ns 1019T ns 1020T Freescale Semiconductor ...

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... The External Interface Module (EIM) is the interface to devices external to the of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown in and Table 12 defines the parameters of signals. Freescale Semiconductor Functional Description and Application Information 3.0 ± 0.3 V Minimum See note 2 ...

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... BCLK (burst clock) ADDR Last Valid Address CS2 R/W LBA EBx (EBC = EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register 30 Read V1 Last Valid Data Read Figure 10. WSC = 1, A.HALF/E.HALF MC9328MXS Technical Data, Rev Freescale Semiconductor ...

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... BCLK (burst clock) Last Valid Address ADDR CS0 R/W LBA OE EB DATA Figure 11. WSC = 1, WEA = 1, WEN = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information V1 Write Data (V1) Last Valid Data Write Last Valid Data MC9328MXS Technical Data, Rev. 3 Unknown V1 Write Data (V1) ...

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... R/W LBA EBx (EBC = EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 12. WSC = 1, OEA = 1, A.WORD/E.HALF 32 Address V1 Read 1/2 Half Word MC9328MXS Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... BCLK (burst clock) ADDR Last Valid Addr CS0 R/W LBA OE EB DATA Figure 13. WSC = 1, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXS Technical Data, Rev. 3 Address 2/2 Half Word ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 14. WSC = 3, OEA = 2, A.WORD/E.HALF 34 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXS Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS3 R/W LBA OE EB DATA Last Valid Data Figure 15. WSC = 3, WEA = 1, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXS Technical Data, Rev. 3 Address 2/2 Half Word ...

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... EBx (EBC =1) weim_data_in Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 16. WSC = 3, OEA = 4, A.WORD/E.HALF 36 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXS Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 17. WSC = 3, WEA = 2, WEN = 3, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXS Technical Data, Rev. 3 Address 2/2 Half Word ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 18. WSC = 3, OEN = 2, A.WORD/E.HALF 38 Last Valid Data Address V1 Read 1/2 Half Word MC9328MXS Technical Data, Rev Word Address 2/2 Half Word Freescale Semiconductor ...

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... EBx (EBC =1) DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 19. WSC = 3, OEA = 2, OEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Last Valid Data Address V1 Read 1/2 Half Word MC9328MXS Technical Data, Rev. 3 ...

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... BCLK (burst clock) ADDR Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 20. WSC = 2, WWS = 1, WEA = 1, WEN = 2, A.WORD/E.HALF 40 Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXS Technical Data, Rev. 3 Unknown Address 2/2 Half Word Freescale Semiconductor ...

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... Last Valid Addr CS2 R/W LBA OE EB DATA Last Valid Data Figure 21. WSC = 1, WWS = 2, WEA = 1, WEN = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Write Data (V1 Word) Last Valid Data Address V1 Write 1/2 Half Word MC9328MXS Technical Data, Rev. 3 Unknown Address ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 22. WSC = 2, WWS = 2, WEA = 1, WEN = 2, A.HALF/E.HALF 42 Nonseq Write V8 Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXS Technical Data, Rev. 3 Write Data Read Data Address V8 Write Write Data Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 23. WSC = 2, WWS = 1, WEA = 1, WEN = 2, EDC = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Read Idle Nonseq Write V8 Last Valid Data Address V1 Read ...

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... ADDR Last Valid Addr CS R/W LBA OE EB DATA Last Valid Data Figure 24. WSC = 2, CSA = 1, WWS = 1, A.WORD/E.HALF 44 Write Data (Word) Last Valid Data Address V1 Write Write Data (1/2 Half Word) MC9328MXS Technical Data, Rev. 3 Address Write Data (2/2 Half Word) Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 25. WSC = 3, CSA = 1, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Nonseq Write V8 Last Valid Data Last Valid Data Address V1 Read Read Data Last Valid Data MC9328MXS Technical Data, Rev ...

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... Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 26. WSC = 2, OEA = 2, CNC = 3, BCM = 1, A.HALF/E.HALF 46 Idle Seq Read V2 Read Data (V1) Address V1 CNC Read Read Data (V1) MC9328MXS Technical Data, Rev. 3 Read Data (V2) Address V2 Read Data (V2) Freescale Semiconductor ...

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... EBx (EBC =1) DATA DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 27. WSC = 2, OEA = 2, WEA = 1, WEN = 2, CNC = 3, A.HALF/E.HALF Freescale Semiconductor Functional Description and Application Information Idle Nonseq Write V8 Last Valid Data Read Data Address V1 ...

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... EBx (EBC = EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 28. WSC = 3, SYNC = 1, A.HALF/E.HALF 48 Nonse Read V5 Address V1 Read V1 Word V2 Word MC9328MXS Technical Data, Rev. 3 Idle Address V5 V5 Word V6 Word Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 29. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.WORD Freescale Semiconductor Functional Description and Application Information Seq Seq Read Read Word V2 Word Address V1 Read V1 Word ...

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... DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 30. WSC = 2, SYNC = 1, DOL = [1/0], A.WORD/E.HALF 50 Seq Read V2 V1 Word Address V1 Read V1 1/2 V1 2/2 MC9328MXS Technical Data, Rev. 3 Idle V2 Word Address V2 V2 1/2 V2 2/2 Freescale Semiconductor ...

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... EBx (EBC =1) ECB DATA Note Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 31. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 2, A.WORD/E.HALF Freescale Semiconductor Functional Description and Application Information Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MXS Technical Data, Rev ...

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... Note 2: EBC = Enable Byte Control bit (bit 11) on the Chip Select Control Register Figure 32. WSC = 7, OEA = 8, SYNC = 1, DOL = 1, BCD = 1, BCS = 1, A.WORD/E.HALF 52 Seq Read Last Valid Data Address V1 Read V1 1/2 V1 2/2 MC9328MXS Technical Data, Rev. 3 Idle V2 V1 Word V2 Word V2 1/2 V2 2/2 Freescale Semiconductor ...

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... Control Register (CONTROLREG1) to match the external SPI master’s timing. In this configuration, SS becomes an input signal, and is used to latch data into or load data out to the internal data shift registers, as well as to increment the data FIFO. master SPI using different triggering mechanisms. Freescale Semiconductor Functional Description and Application Information T1 T3 ...

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... Figure 36. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger SS (input) SCLK, MOSI, MISO Figure 37. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT SS (input) 6 SCLK, MOSI, MISO Figure 38. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge MC9328MXS Technical Data, Rev. 3 Freescale Semiconductor ...

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... This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD controller with various display configurations, refer to the LCD controller chapter of the MC9328MXS Reference Manual. LSCLK LD[15:0] Figure 40. SCLK to LD Timing Diagram Freescale Semiconductor Functional Description and Application Information Figure 34 through Parameter Minimum 2T 3 • ...

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... T4 T6 XMAX T8 (1,1) (1,2) (1,X) T9 T10 Minimum T5+T6 +T7+T9 XMAX MC9328MXS Technical Data, Rev. 3 Maximum Unit 2 ns Display region Line 1 Line Y T7 Corresponding Register Value Unit (VWAIT1·T2)+T5+T6+T7+T9 Ts XMAX+T5+T6+T7+T9+T10 Ts VWIDTH·(T2) Ts VWAIT2·(T2) Ts HWIDTH+1 Ts HWAIT2+1 Ts HWAIT1+1 Ts Freescale Semiconductor ...

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... The output is available at the pulse-width modulator output (PWMO) external pin. Its timing diagram is shown in Figure 42 and the parameters are listed in System Clock PWM Output Figure 42. PWM Output Timing Diagram Freescale Semiconductor Functional Description and Application Information Minimum Corresponding Register Value - ...

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... Controller. 58 1.8 ± 0.1 V Minimum Maximum Minimum 0 87 3.3 – 7.5 – – 5 – 6.67 5.7 – 5.7 – MC9328MXS Technical Data, Rev. 3 3.0 ± 0.3 V Unit Maximum 0 100 MHz 5/10 – ns 5/10 – ns – 5/10 ns – 5/ – – ns Freescale Semiconductor ...

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... SDRAM clock high-level width 2 SDRAM clock low-level width 3 SDRAM clock cycle time 3S CS, RAS, CAS, WE, DQM setup time 3H CS, RAS, CAS, WE, DQM hold time 4S Address setup time 4H Address hold time 5 SDRAM access time ( Freescale Semiconductor Functional Description and Application Information COL/ Data Note: CKE is high during the read/write cycle ...

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... V Minimum Maximum – 6.84 – 22 2.85 – – 6.84 – 6.84 – – t RCD ROW/BA 8 MC9328MXS Technical Data, Rev. 3 3.0 ± 0.3 V Unit Minimum Maximum – – 2.5 – ns – – – – ns RCD1 COL/BA 9 DATA Freescale Semiconductor ...

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... SDRAM clock cycle time. These settings can be found in the MC9328MXS reference manual. RP RCD SDCLK RAS CAS ADDR DQ DQM Figure 45. SDRAM Refresh Timing Diagram Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 2.67 – 6 – 11.4 – 3.42 – 2.28 – 2 – ...

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... Figure 46. SDRAM Self-Refresh Cycle Timing Diagram 62 1.8 ± 0.1 V Minimum Maximum 2.67 – 6 – 11.4 – 3.42 – 2.28 – 1 – – RC1 MC9328MXS Technical Data, Rev. 3 3.0 ± 0.3 V Unit Minimum Maximum 4 – – – – – – ns RP1 t – ns RC1 Freescale Semiconductor ...

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... USBD_ROE active to USBD_VPO low ROE_VPO USBD_ROE active to USBD_VMO high ROE_VMO USBD_VPO high to USBD_ROE deactivated VPO_ROE USBD_VMO low to USBD_ROE deactivated (includes SE0) VMO_ROE Freescale Semiconductor Functional Description and Application Information 6 t PERIOD 2 MC9328MXS Technical Data, Rev VMO_ROE 3 t VPO_ROE t FEOPT 5 3.0 ± 0.3 V ...

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... C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction, Slave Acknowledge, Data, Data Acknowledge, and STOP. 64 Parameter Minimum 82 MC9328MXS Technical Data, Rev. 3 3.0 ± 0.3 V Unit Minimum Maximum 160.00 175.00 ns 11.97 12.03 Mb FEOPR 3.0 ± 0.3 V Unit Maximum – ns Freescale Semiconductor ...

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... Use of the gated clock is not allowed in network mode. These distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices. Freescale Semiconductor Functional Description and Application Information 5 3 ...

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... STFS (bl) Output STFS (wl) Output STXD Output SRXD Input Note: SRXD input in synchronous mode only. Figure 50. SSI Transmitter Internal Clock Timing Diagram SRCK Output SRFS (bl) Output SRFS (wl) Output SRXD Input Figure 51. SSI Receiver Internal Clock Timing Diagram MC9328MXS Technical Data, Rev Freescale Semiconductor ...

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... Table 29. SSI (Port C Primary Function) Timing Parameter Table Ref No. Parameter Internal Clock Operation 1 1 STCK/SRCK clock period 2 STCK high to STFS (bl) high 3 SRCK high to SRFS (bl) high 3 4 STCK high to STFS (bl) low 5 SRCK high to SRFS (bl) low Freescale Semiconductor Functional Description and Application Information 1.8 ± ...

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... Freescale Semiconductor ...

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... STCK high to STXD high 11b STCK high to STXD low 12 STCK high to STXD high impedance 13 SRXD setup time before SRCK low 14 SRXD hold time after SRCK low Freescale Semiconductor Functional Description and Application Information 1.8 ± 0.1 V Minimum Maximum 1.14 – 0 – ...

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... MC9328MXS Technical Data, Rev. 3 3.0 ± 0.3 V Unit Minimum Maximum 2 ) 81.4 – ns 40.7 – ns 40.7 – 81.4 ns 16.6 25.5 ns 8.1 18.2 ns 9.3 18.7 ns 15.7 26.1 ns 1.0 – – 16.5 – – 1.0 – – ns Freescale Semiconductor ...

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... Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: i.MXS Product Family Table 31. i.MXS 225 MAPBGA Pin Assignments ...

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... SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A. 4. DATUM A, THE SEATING PLANE IS DEFINED BY SPHERICAL CROWNS OF THE SOLDER BALLS. 5.PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE Figure 54. i.MXS 225 MAPBGA Mechanical Drawing 72 Case Outline 1304B MC9328MXS Technical Data, Rev. 3 SIDE VIEW Freescale Semiconductor ...

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... MC9328MXS Product Brief (order number MC9328MXSP) MC9328MXS Reference Manual (order number MC9328MXSRM) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. The ARM Ltd. documentation is available from http://www ...

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... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...