TS68882VR16 E2V, TS68882VR16 Datasheet - Page 33

• Manufacturer Part Number: TS68882VR16
• Manufacturer: E2V

Specifications of TS68882VR16

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

8.23
8.23.1
8.23.2
e2v semiconductors SAS 2007
Data Strobe (DS)
Data Transfer and Size Acknowledge (DSACK0, DSACK1)
Reset (RESET)
This active-low input signal indicates that there is valid data on the data bus during a write bus cycle.
These active-low, three-state output signals indicate the completion of a bus cycle to the main proces-
sor. The TS68882 asserts both the DSACK0, and DSACK1 signals upon assertion of CS.
If the bus cycle is a main processor read, the TS68882 asserts DSACK0 and DSACK1 signals to indicate
that the information on the data bus is valid. (Both DSACK signals may be asserted in advance of the
valid data being placed on the bus). If the bus cycle is a main processor write to the TS68882, DSACK0
and DSACK1 are used to acknowledge acceptance of the data by the TS68882.
The TS68882 also uses DSACK0 and DSACK1 signals to dynamically indicate to the TS68020/TS68030
the “port” size (system data bus width) on a cycle-by-cycle basis. Depending upon which of the two
DSACK pins are asserted in a given bus cycle, the TS68020/TS68030 assumes data has been trans-
ferred to/from an 8-, 16-, or 32-bit wide data port.
the TS68882 for the various bus cycles over the various bus cycles over the various system data bus
configurations.
Table 8-5
TS68882 implements all 16-bit co-processor interface registers on data lines D16 - D13 (to eliminate the
need for on-chip multiplexers); however, the TS68020/TS68030 expects 16-bit registers that are located
in a 32-bit port at odd word addresses (A1 = 1) to be implemented on data lines D0-D15. For accesses to
these registers when configured for 32-bit bus operation, the TS68882 generates DSACK signals as
listed in
An external holding resistor is required to maintain both DSACK0 and DSACK1 high between bus
cycles. In order to reduce the signal rise time, the DSACK0 and DSACK1 lines are actively pulled up
(negated) by the TS68882 following the rising edge of AS or DS and both DSACK lines are then three-
stated (placed in the high-impedance state) to avoid interference with the next bus cycle.
Table 8-5.
This active-low input signal causes the TS68882 to initialize the floating-point data registers to non-sig-
naling not-a-numbers (NANs) and clears the floating-point control, status, and instruction address
registers.
When performing a power-up reset, external circuitry should keep the RESET line asserted to a mini-
mum of four clock cycles after V
when power is applied. For compatibility with all TS68000 Family devices, 100 milliseconds should be
used as the minimum.
Data Bus
32-bit
32-bit
16-bit
8-bit
All
Table 8-5
indicates that all accesses over a 32-bit bus where A4 equals zero are to 16-bit registers. The
DSACK Assertions
to inform the TS68020/TS68030 of valid data on D16 - D31 instead of D0-D15.
A4
1
0
x
x
x
DSACK1
CC
H
H
L
L
L
is within tolerance. This assures correct initialization of the TS68882
DSACK2
H
H
H
L
L
Table 8-5
Comments
Valid data on D31-D0
Valid data on D31-D16
Valid data on D31-D16 or D15-D0
Valid data on D31-D24, D23-D16, D15-D8, D7-D0
Insert Wait States in Current Bus Cycle
lists the DSACK assertions that are used by
0852B–HIREL–06/07
TS68882
33