TS68882VR16 E2V, TS68882VR16 Datasheet - Page 22

• Manufacturer Part Number: TS68882VR16
• Manufacturer: E2V

Specifications of TS68882VR16

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

TS68882
Figure 8-7.
Typical Co-processor Configuration
8.2
Bus Interface Unit
All communications between the TS68020/TS68030 and the TS68882 occur via standard TS68000
Family bus transfers. The TS68882 is designed to operate on 8-, 16-, or 32-bit data buses.
The TS68882 contains a number of co-processor interface registers (CIRs) which are addresses in the
same manner as memory by the main processor. The TS68000 Family co-processor interface is imple-
mented via a protocol of reading and writing to these registers by the main processor. The TS68020 and
TS68030 implements this general- purpose co-processor interface protocol in hardware and microcode.
When the TS68020/TS68030 detects a typical TS68882 instruction, the MPU writes the instruction to the
memory-mapped command CIR, and reads the response CIR. In this response, the BIU encodes
requests for any additional action required of the MPU on behalf of the TS68882. For example, the
response may request that the MPU fetch an operand from the evaluated effective address and transfer
the operand to the operated CIR. Once the MPU fulfills the co-processor request(s), it is free to fetch and
execute subsequent instructions.
A key concern in a co-processor interface that allows concurrent instruction execution is synchronization
during main processor and co-processor communication. If a subsequent instruction is written to the
TS68882 before the CCU has passed the operands for the previous instructions to the ECU, the
response instructs the TS68020/TS68030 to wait. Thus, the choice of concurrent or nonconcurrent
instruction execution is determined on an instruction-by-instruction basis by the co-processor.
The only difference between a co-processor bus transfer and any other bus transfer is that the
TS68020/TS68030 issues a function code to indicate the CPU address space during the cycle (the func-
tion codes are generated by the TS68000 Family processors to identify eight separate address spaces).
Thus, the memory-mapped co-processor interface registers do not infringe upon instruction or data
address spaces. The TS68020/TS68030 places a co-processor ID field from the co-processor instruction
onto three of the upper address lines during co-processor accesses. This ID, along with the CPU
address space function code, is decoded to select one of eight co-processors in the system.
Since the co-processor interface protocol is based solely on bus transfers, the protocol is easily emu-
lated by software when the TS68882 is used as a peripheral with any processor capable of memory-
mapped I/O over on TS68000 style bus.
22
0852B–HIREL–06/07
e2v semiconductors SAS 2007