STPCI2HDYI STMicroelectronics, STPCI2HDYI Datasheet - Page 93

• Manufacturer Part Number: STPCI2HDYI
• Manufacturer: STMicroelectronics

Specifications of STPCI2HDYI

• Operating Temperature (min): -40C
• Operating Temperature (max): 115C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 2.45/3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.7/3.6V
• Package Type: BGA
• Screening Level: Industrial
• Pin Count: 516
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Supplier Unconfirmed

The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew
between the outputs. The delay through the buffer
is not important so it does not have to be a zero
delay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed can
vary between PCB layers, the clocks should be
routed in a consistent way. The routing to the
STPC memory input should be longer by 75 mm to
compensate for the extra clock routing on the
DIMM. Also a 20 pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace
impedance (60-75 ohms)
the clocks should be routed with spacing to
adjacent tracks of at least twice the clock trace
width. For designs which use SDRAMs directly
mounted on the motherboard PCB all the clock
trace lengths should be matched to the constraints
given in
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two single-
row DIMMs or one dual-row DIMM can be
controlled.
Figure 6-24. Recommended topology for 4 on-board SDRAMs (IBIS model)
MCLKO
MCLKI
Track impedance= 75 Ohms
Trace thickness = 0.72 mil
Trace width = 4 to 8 mils
Figure 6-23
and in
400 mils
.
To minimise crosstalk
Section 4.5.3.
400 mils
.
18 Ohms
6.4.3.4. Summary
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
Using a low impedance such as 50Ω for these
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial for
the other signals but if their timing is not as critical
as the address/control signals they could use the
default value. Using a lower impedance implies
using wider traces which may have an impact on
the routing of the board.
The layout of this interface can be validated by an
electrical
available on the STPC web site.
6.5. CLOCK TOPOLOGY FOR ON-BOARD
Figure 4-5
clock topology and the resulting IBIS simulation in
the case of four on-board SDRAM devices and no
clock buffer.
SDRAM
and
simulation
3500 mils
3500 mils
3500 mils
3500 mils
Figure 6-25
using
give the recommended
the IBIS
STPC® ATLAS
MCLK0
MCLK1
MCLK2
MCLK3
model
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