STPCI2HDYI STMicroelectronics, STPCI2HDYI Datasheet - Page 24

• Manufacturer Part Number: STPCI2HDYI
• Manufacturer: STMicroelectronics

Specifications of STPCI2HDYI

• Operating Temperature (min): -40C
• Operating Temperature (max): 115C
• Processing Unit: Microprocessor
• Operating Supply Voltage (min): 2.45/3V
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 2.7/3.6V
• Package Type: BGA
• Screening Level: Industrial
• Pin Count: 516
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Supplier Unconfirmed

STPC® ATLAS
RMRTCCS# ROM/Real Time clock chip select.
This pin is a multi-function pin. This signal is
asserted if a ROM access is decoded during a
memory cycle. It should be combined with MEMR#
or MEMW# signals to properly access the ROM.
During an IO cycle, this signal is asserted if access
to the Real Time Clock (RTC) is decoded. It should
be combined with IOR# or IOW# signals to
properly access the real time clock.
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC
Atlas using ISACLK and ISACLKX2 as the input
selection strobes.
Note that IRQ8B, which by convention is
connected to the RTC, is inverted before being
sent to the interrupt controller, so that it may be
connected directly to the IRQ# pin of the RTC.
ISAOE# Bidirectional OE Control. This signal
controls the OE signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
KBCS# Keyboard Chip Select. This signal is
asserted if a keyboard access is decoded during a
I/O cycle.
ZWS# Zero Wait State. This signal, when asserted
by addressed device, indicates that current cycle
can be shortened.
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Atlas before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA
Request. These are the ISA bus DMA request
signals. They are to be encoded before connection
to the STPC Atlas using ISACLK and ISACLKX2
as the input selection strobes.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
2.2.5. PCMCIA INTERFACE
RESET Card Reset. This output forces a hard
reset to a PC Card.
A[25:0] Address Bus. These are the 25 low bits of
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA
bus owns the bus and are outputs at all other
times.
D[15:0] I/O Data Bus (PCMCIA). These are the
external PCMCIA databus pins.
24/108
1
IORD# I/O Read. This output is used with REG# to
gate I/O read data from the PC Card, (only when
REG# is asserted).
IOWR# I/O Write. This output is used with REG#
to gate I/O write data from the PC Card, (only
when REG# is asserted).
WP Write Protect. This input indicates the status of
the Write Protect switch (if fitted) on memory PC
Cards (asserted when the switch is set to write
protect).
BVD1, BVD2 Battery Voltage Detect. These
inputs will be generated by memory PC Cards that
include batteries and are an indication of the
condition of the batteries. BVD1 and BVD2 are
kept asserted high when the battery is in good
condition.
READY#/BUSY#/IREQ#
request. This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
WAIT# Bus Cycle Wait. This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
OE# Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
WE#/PRGM# Write Enable. This output is used by
the host for gating Memory Write data. WE# is also
used
programmable memory.
REG# Attribute Memory Select. This output is
inactive (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only
respond to IORD# or IOWR# when REG# is active
(low). Also see
CD1#, CD2# Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
Card therefore they will be forced low whenever a
card is inserted in a socket.
CE1#, CE2# Card Enable. These are active low
output signals provided from the PCIC. CE#1
enables even Bytes, CE#2 odd Bytes.
ENABLE# Enable. This output is used to activate/
select a PC Card socket. ENABLE# controls the
external address buffer logic.C card has been
detected (CD#1 and CD#2 = '0').
for
memory
Section 2.2.7.
PC
Ready/busy/Interrupt
Cards
that
have