MC10XS3435DPNAR2 Freescale, MC10XS3435DPNAR2 Datasheet - Page 36

• Manufacturer Part Number: MC10XS3435DPNAR2
• Manufacturer: Freescale

Specifications of MC10XS3435DPNAR2

• Switch Type: High Side
• Power Switch Family: MC10XS3435
• Input Voltage: -0.3 to 5.8V
• Output Current: 6A
• Number Of Outputs: 4
• Mounting: Surface Mount
• Supply Current: 6.5mA
• Package Type: PQFN EP
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Pin Count: 24
• Lead Free Status / RoHS Status: Compliant

ADDRESS XX000 — STATUS REGISTER
(STATR_S)
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO
data. In addition to the device status, this feature provides the
ability to read the content of the PWMR_s, CONFR0_s,
CONFR1_s, OCR_s, GCR and CALR registers (Refer to the
section entitled
Return Data) on page
ADDRESS A
REGISTER (PWMR_S )
of corresponding output through the SPI. Each output “s” is
independently selected for configuration based on the state
of the D14 : D13 bits
current protection profile: the over-current thresholds are
divided by 2 and, the inrush and cooling responses are
dedicated to 28 W lamps for HS[0,1] outputs. This bit it not
taken into account for HS[2,3] outputs.
corresponding output switch and a logic [0] turns it OFF (if IN
input is also pulled down). Bits D6:D0 set the output PWM
duty-cycle to one of 128 levels for PWM_en is set to logic [1],
as shown
ADDRESS A
REGISTER (CONFR0_S )
corresponding output switching through the SPI. Each output
“s” is independently selected for configuration based on the
state of the D14 : D13 bits
will enable the output for direct control. A logic [1] on bit D5
will disable the output from direct control (in this case, the
output is only controlled by On bit).
or medium or low speed slew rate for the selected output, the
36
10XS3435
Table 12. Output Selection
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
The STATR register is used to read the device status and
The PWMR_s register allows the MCU to control the state
A logic [1] on bit D8 (28 W_s) selects the 28 W over-
Bit D7 sets the output state. A logic [1] enables the
The CONFR0_s register allows the MCU to configure
For the selected output, a logic [0] on bit D5 (DIR_DIS_s)
D4:D3 bits (SR1_s and SR0_s) are used to select the high
A
1
(D14)
0
0
1
1
Table
1
1
Serial Output Communication (Device Status
A
A
7, page 29.
0
0
001— OUTPUT PWM CONTROL
010— OUTPUT CONFIGURATION
(Table
38.
(Table
A
12).
0
(D13)
0
1
0
1
12).
HS Selection
HS0 (default)
HS1
HS2
HS3
default value [00] corresponds to the medium speed slew rate
(Table
that will be delayed of predefined PWM clock rising edges
number, as shown
PWM_en bit is set to logic [1]).
ADDRESS A
REGISTER (CONFR1_S)
corresponding output fault management through the SPI.
Each output “s” is independently selected for configuration
based on the state of the D14 : D13 bits
autoretry counter for the selected output, the default value [1]
corresponds to enable auto-retry feature without time
limitation.
for the selected output, the default value [0] corresponds to
enable this feature.
shorted to VPWR protection for the selected output, the
default value [0] corresponds to enable this feature.
open-load detection for the selected output, the default value
[0] corresponds to enable this feature
output open-load detection for the selected output, the
default value [0] corresponds to enable this feature.
open-load detection for LEDs for the selected output, the
default value [0] corresponds to ON output open-load
detection is set for bulbs
Table 13. Slew Rate Speed Selection
Table 14. ON Open-load Selection
OLON_dis_s (D3) OLLED_en_s (D1) ON OpenLoad detection
Incoming message bits D2 : D0 reflect the desired output
The CONFR1_s register allows the MCU to configure
A logic [1] on bit D6 (RETRY_unlimited_s) disables the
A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry
A logic [1] on bit D4 (OS_dis_s) disables the output hard
A logic [1] on bit D3 (OLON_dis_s) disables the ON output
A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF
A logic [1] on bit D1 (OLLED_en_s) enables the ON output
SR1_s (D4)
13).
0
0
1
0
0
1
1
1
A
0
011 — OUTPUT CONFIGURATION
Table
Analog Integrated Circuit Device Data
SR0_s (D3)
(Table
8, page
0
1
X
0
1
0
1
14).
29
Freescale Semiconductor
enable with bulb threshold
enable with LED threshold
(only available for
(Table
(Table
Slew Rate Speed
medium (default)
(default)
disable
14).
Not used
12).
high
low